Vipul Kumar Singhal

Optimal Gate Size Selection for Standard Cells in a Library

Standard cell libraries provide designers with a fixed set of well characterized logic blocks. As designs are pushed for high performance, low area, and low power, it is essential to have a, good standard cell library that can help achieve these goals. As gate sizing is crucial to timing, the number of gate sizes (drive strengths) available for each of the primitives is an important factor to be considered. While an infinite granularity of gate sizes is preferable to get the best entitlement, it is often impractical due to the huge cost associated with developing and maintaining libraries. It is therefore essential to find ways to achieve the best performance, power and area, with a, reasonable library size. In this paper we focus on the problem of finding out the optimal ratio of gate sizes to be selected. 65nm libraries were used for validating the claims on a real design and the results are presented in this paper

A Methodology for Early and Accurate Analysis of Inrush and Latency Tradeoffs during Power-Domain Wakeup

Power gating is used in almost all Low-power devices to lower leakage. In this power gating, the three important design parameters are the domain-wakeup latency (from sleep to active mode transition) time, the inrush-current when the power switches are turned on, and the voltage dip caused by the inrush current. Also, the analysis of these parameters has some uniqueness when there is an on-die power-supply system. In this paper we present a methodology for analyzing these parameters, followed by a case study involving analysis of all these parameters using circuit simulation (SPICE) for a wakeup latency critical low power SoC (System on a Chip).