Rajesh N. Gupta

A novel capacitor-less DRAM cell using thin capacitively-coupled thyristor (TCCT)

A capacitor-less DRAM cell using a thin capacitively-coupled thyristor (TCCT DRAM) is introduced. Experimental results from unit memory cell fabricated in a 130nm SOI logic technology demonstrate Ion/Ioff ratio of 107, non-destructive read; write speed less than 2ns at 125C, and solid retention characteristics. These cell characteristics combined with a small cell area (as low as 9F2) and simple process integration make TCCT DRAM a suitable candidate for high-performance high-density embedded or standalone memory applications

Reliability of thyristor-based memory cells

This is the first published study of the reliability of Thyristor-based high-speed memories. The T-RAM (Thyristor-based Random Access Memory) was characterized using test structures and multi-megabit product die fabricated in a 130nm SOI logic technology. The reliability lifetime of a nominal bit was investigated by subjecting TCCT devices (Thin Capacitively Coupled Thyristor) to a DC current stress. The resulting acceleration model yields a lifetime of 1.0E+40 yrs for the Data-1 state and 1.0E+5 yrs for the Data-0 state. These long lifetimes are consistent with the 26 FIT long-term failure rate found for 9 Mb arrays, from dynamic lifetest on 9Mb & 18Mb T-RAM product die having full SRAM functionality. The susceptibility of T-RAM arrays to soft errors was assessed by accelerated neutron testing, and accelerated alpha testing, of 9Mb T-RAM product die as well as 9Mb SRAM product die from three suppliers. n-SER for the T-RAM is 610 FIT/Mb, better than the average of 700 FIT/Mb for 6T SRAM technology. Exposure of the T-RAM product die to X-rays showed that they tolerate doses of 450 rad or more (3–4x the dose for X-ray inspections) without degradation of nominal TCCT retention times, and without functional failure of memory cells. Taken together, the results of this study shows that T-RAM is a reliable memory technology.

32nm high-density high-speed T-RAM embedded memory technology

Thyristor Random Access Memory (T-RAM) is an ideal candidate for application as an embedded memory due to its substantially better density vs. performance tradeoff and logic process compatibility [1–3]. T-RAM memory embedded in a 32nm logic process with read and write times of 1ns and a bit fail rate less than 0.5ppm is reported for the first time. T-RAM memory cell median read current of 250µA/cell at 1.2V with an Ion/Ioff current ratio of more than 108 is demonstrated at 105°C. Robust margins to dynamic disturb due to the access (read/write) of neighboring bits in the memory array have also been verified.

Fully planar 0.562/spl mu/m/sup 2/ T-RAM cell in a 130nm SOI CMOS logic technology for high-density high-performance SRAMs

Major advancements in T-RAM cell manufacturability are reported. A fully planar implementation of a T-RAM cell is presented, which is easily integrated into a baseline 130nm SOI CMOS logic technology by adding photo-mask and ion-implantation steps. The cell area of 0.562/spl mu/m/sup 2/ (33F/sup 2/) is four times smaller than conventional 6T-SRAM. A new scheme, called Restore, significantly improves control of the cell standby current. Excellent T-RAM cell temperature stability is demonstrated between 0/spl deg/C and 125/spl deg/C. Measurement results from a 9Mb T-RAM test chip with full SRAM functionality show good bit yield, 2ns cell write speed, 1.7ns cell read speed, and a cell standby current of /spl sim/1nA/cell.