Farid Nemati

A novel high density, low voltage SRAM cell with a vertical NDR device

A novel 8F/sup 2/ NDR-based cell for giga-scale SRAMs on silicon substrates is presented. The new SRAM cell uses a thin vertical PNPN structure with gate-assisted turn-off and turn-on mechanisms. Experimental measurements show standby cell currents lower than 10 pA//spl mu/m/sup 2/, switching speeds faster than 40 ns, and operating voltages as low as 1.5 V. An SRAM based on this new cell is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. To our knowledge, this cell has the lowest standby power consumption reported so far for an NDR-based SRAM cell either on silicon or on III-V substrates.

A novel pillar DRAM cell for 4 Gbit and beyond

A novel structure and fabrication process for a DRAM cell for 4 Gbit and beyond is proposed. A poly-Si pillar transistor is formed on top of a trench capacitor with the top of the pillar transistor being directly connected to the bit line. In order to reduce the process steps, word line formation by a spacer etch and self-aligned bit line contact using CMP process are developed. XTEM micrographs show almost single grain and less defect in the small pillars after crystallization annealing of prepatterned /spl alpha/-Si. Electrical measurements show that the pass transistor has good subthreshold slope and Id-Vd characteristics. Improvements in the device performance has been achieved by a sacrificial oxidation and hydrogenation.