Hyun-jin Cho

A novel capacitor-less DRAM cell using thin capacitively-coupled thyristor (TCCT)

A capacitor-less DRAM cell using a thin capacitively-coupled thyristor (TCCT DRAM) is introduced. Experimental results from unit memory cell fabricated in a 130nm SOI logic technology demonstrate Ion/Ioff ratio of 107, non-destructive read; write speed less than 2ns at 125C, and solid retention characteristics. These cell characteristics combined with a small cell area (as low as 9F2) and simple process integration make TCCT DRAM a suitable candidate for high-performance high-density embedded or standalone memory applications

Novel DRAM cell with amplified capacitor for embedded application

Novel DRAM cell with logic process compatible and whose memory operation is the same as the conventional DRAM operation is first time introduced. The cell uses the MOS capacitor with open base NPN bipolar transistor to amplify the storage capacitor. We fabricated the prototype cell and demonstrated the memory cell operation.

32nm high-density high-speed T-RAM embedded memory technology

Thyristor Random Access Memory (T-RAM) is an ideal candidate for application as an embedded memory due to its substantially better density vs. performance tradeoff and logic process compatibility [1–3]. T-RAM memory embedded in a 32nm logic process with read and write times of 1ns and a bit fail rate less than 0.5ppm is reported for the first time. T-RAM memory cell median read current of 250µA/cell at 1.2V with an Ion/Ioff current ratio of more than 108 is demonstrated at 105°C. Robust margins to dynamic disturb due to the access (read/write) of neighboring bits in the memory array have also been verified.

Fully planar 0.562/spl mu/m/sup 2/ T-RAM cell in a 130nm SOI CMOS logic technology for high-density high-performance SRAMs

Major advancements in T-RAM cell manufacturability are reported. A fully planar implementation of a T-RAM cell is presented, which is easily integrated into a baseline 130nm SOI CMOS logic technology by adding photo-mask and ion-implantation steps. The cell area of 0.562/spl mu/m/sup 2/ (33F/sup 2/) is four times smaller than conventional 6T-SRAM. A new scheme, called Restore, significantly improves control of the cell standby current. Excellent T-RAM cell temperature stability is demonstrated between 0/spl deg/C and 125/spl deg/C. Measurement results from a 9Mb T-RAM test chip with full SRAM functionality show good bit yield, 2ns cell write speed, 1.7ns cell read speed, and a cell standby current of /spl sim/1nA/cell.

Correlation of I d - and I g -random telegraph noise to positive bias temperature instability in scaled high-κ/metal gate n-type MOSFETs

Random telegraph noise (RTN) in high-κ nMOSFETs is directly linked to Positive Bias Temperature Instability (PBTI). For the first time, the correlation between I<inf>d</inf>- and I<inf>g</inf>-RTN is clearly observed in high-κ MOSFET. I<inf>g</inf>-RTN is directly related to physical trapping or de-trapping and the I<inf>d</inf>-RTN reflects sensitivity to charge trapping as determined by gm, which is confirmed by both experiments and TCAD simulations.