Rajesh Tiwari

A generic low power scan chain wrapper for designs using scan compression

Shrinking power budgets in low power system-on-chips (SoCs) have elevated test power consumption as a major consideration for chip design and test engineering teams. Many traditional automatic test pattern generation (ATPG) and design-for-test (DFT) techniques for test power reduction are either effective for circuits not using test data compression hardware or have implications on the physical design cycle. This paper describes a technique for reducing peak current during scan based testing that can work in the presence of compression, and impose no restrictions on physical design, e.g. related to chip clocking. We propose low-design effort modifications to the test compression logic (wrapper-like changes) that enable us to (a) bypass scan chains or groups of them and (b) shift in constant values into the bypassed flip-flops for lowering the instantaneous current drawn. The modifications are easily localized to a scan chain wrapper that can be used with any scan compression solution. An SoC using lowpower scan chain wrappers provides sufficient configurability (scan chains bypassed or scan chains included) to explore different power reductions with test cost trade-offs. We describe a methodology that allows us to manage the inherent configurability available in our solution. For empirical validation, we have implemented low-power scan chain wrappers for a subset of scan chains in a recently taped-out 65nm low-power SoC. We present experimental data from ATPG and initial silicon power measurements for this chip to demonstrate the benefits and limitations of the proposal.

Methodology for Early RTL Testability and Coverage Analysis and Its Application to Industrial Designs

Testability analysis in the RTL design cycle of an IP or SoC is a critical need for designers to minimize design iterations and resources, and to enable faster design closure times. A mandatory requirement for any such technique is its scalability and applicability to large and complex industrial designs. In this paper, we share an RTL testability analysis framework developed to address the above need. The framework consists of three main components: (i) A strong static design rules for testability checker that can audit an RTL circuit for DFT readiness from both stuck-at and transition fault testing perspectives, (ii) Coverage estimator that can provide early bounds for achievable coverage and help pinpoint design artifacts that limit coverage, and (iii) A random pattern based analysis engine to identify hard-to-test nodes that warrant further fixes. This framework has been commercially used by multiple customers. In collaboration with one of our customers, we share empirical data from applying this methodology to various IPs in a recently taped-out 45nm SoC.

A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips

Conventional methods to assess the test data volume (TDV) of logic in system-on-chips (SoCs) use intuitive formulae that are often agnostic of the target automatic test equipment (ATE) hardware or the ATE test program compilation process. In this paper, we first show that such ATE-unaware approaches lead to a significant gap between these estimates and the actual tester memory consumed. We also provide a generic solution to this problem by using statistical regression techniques to build an ATE-aware TDV model that accurately estimates test program memory consumption as a function of the design and test pattern characteristics. We have implemented this methodology using an off-the-shelf regression solver in the context of a production test flow. We show that the estimator can be used to compute TDV with very high accuracy for logic tests of various industrial IP cores and SoCs.