Rajiv Kumaran

Design of high precision electronics for laser range finder

Resolution of Time to Digital Convertor (TDC) is a critical parameter in determining the overall performance of Time Of Flight based laser range finder system. This paper focuses on designing a high resolution Laser Range Finder (LRF) using Commercial-Off-The-Shelf (COTS) components. The designed LRF consists of a high resolution Time to Digital Convertor using Virtex-4 FPGA, Parallel to USB converter, High Voltage Power Supply and Data acquisition and display module. TDC generates START pulse at pulse repetition frequency (prf). This pulse is fed as trigger to laser TX. Avalanche Photo-Diode (APD) receiver with high voltage bias (~140V) generates a STOP pulse on receipt of reflected laser beam. This pulse is level translated and fed to TDC as STOP pulse. Digital Clock Manager (DCM) is used to achieve clock interpolation for improving resolution beyond 1 clock period. The output of TDC is parallel 16-bit digital count which is converted to serial USB protocol and interfaced to PC based data acquisition system. The raw data is processed and distance information is derived after calibration with known distance sets. Graphical User Interface (GUI) is developed for display, record and calibration. Full system resolution of about 22 cm is achieved in hardware for a range of 10m. The system has a power consumption of 6.15W.

An all digital delay lock loop architecture for high precision timing generator

Remote sensing satellites use Charge Coupled Detectors (CCD) to achieve lower noise and higher dynamic range. Operation of a CCD requires high precision clocks/sequences. Generally it is achieved by using Phase Locked loop (PLL) or Delay Lock Loop (DLL). DLL are preferred for their low noise. An All Digital Delay Lock Loop (ADDLL) is designed to be used in the timing generation core. It is implemented using RTL design flow. This paper discusses design and implementation of an All Digital Delay lock loop suitable for implementation using RTL design methodology. It shows detailed blocks and implementation. It also discusses the challenges faced and their solutions in using RTL design for implementing this DLL. The resolution achieved was 620 ps in 180nm technology with phase error of 232 ps.

Design of low power, low noise & miniaturized electronics for methane sensors for mars

Indias future science vision emphasizes planetary explorations for better understanding of the universe, finding new domains of material resources, energy, environmental systems and habitat. Mars has a special significance of having many similarities with Earth. Methane Sensor for Mars (MSM) is one of the significant payloads of Indias first mars mission. The prime objective of the proposed Methane (CH4) Sensor for Mars (MSM) is to measure concentration of methane in the Martian atmosphere. The sensor configurations were worked out keeping in mind the mission requirements for low weight & power, while ensuring all the performance goals are met. This paper presents the design and development of low power miniaturized Proximity electronics module for MSM. The key challenges in the design of Proximity front end electronics are very low noise precision bias generator, low noise current to voltage conversion and low noise digitizer prior to final data. Proximity electronics also performs the function of temperature control of detectors and etalons. The proposed Proximity electronics system is modular catering to two channels realized in a low power, weight & size tray package. Proximity Electronics is realized in less than 500g and consumes power <;4W.

Generic and programmable Timing Generator for CCD detectors

Charge Coupled Devices (CCD) detectors are frequently used in imaging payloads developed for different satellite applications like space based astronomy and earth observations. CCDs are being used for onboard/satellite applications as it provides lower noise and higher dynamic range than CMOS detectors. CCDs are available in various architectures hence design of Timing Generator is planned based on CCD requirements. This paper discusses design methodology for generic timing generator which is completely programmable and supports various CCD architectures. The aim of design is to provide flexibility in terms of number of different types of clocks, effective image area and readout features with respect to various CCD architectures. Different supported CCD architectures, overall clock requirements, required readout features are studied and design architecture is worked out. The RTL design of Timing Generator is done using VHDL and block level verification is done using Verilog. The design is targeted to Xilinx Virtex-6 LX FPGA.