Sanjeev Mehta

Indigenous development of SERDES interface for miniaturization

In satellite systems, large amount of high speed data is required to be transmitted from one system to another. Conventional parallel data transmission requires a large number of cables/interface-packages and results in large weight and volume. Parallel interface in a typical future camera system requires >8000 cables between camera electronics and data handling system. In addition, with increase in transmission rate, problems associated with crosstalk become more critical. One possible solution identified is serial interface, also termed as SERDES (Serializer/DESerializer) interface. A typical SERDES interface comprises of encoder/decoder, PLL, timing-control and multiplexer/de-multiplexer. Encoding of serial data solves high speed serial data transmission problems by incorporating clock embedding, DC balancing, sync info insertion and error detection. DC balancing also solves the issue of Inter-Symbol Interference (ISI). Available SERDES interface devices have limitations like poor reduction factor, no clock embedding or non-availability of space qualified part. Hence, an attempt is made to understand and implement this interface with a goal of indigenous SERDES ASIC development, which will also overcome the above issues. Various serial encoding techniques are surveyed and 8B/10B encoding technique is finalized for very high speed serial data transmission. As an initial step, 8B/10B encoding based SERDES interface is implemented in a FPGA. Final serial data rate achieved is 250Mbps, which corresponds to transmission of 8-bit at 25MSPS and reduces interfaces by a factor of 8. Higher factors will be achieved by design with new encoding techniques like 12B/14B. This paper discusses different SERDES interfaces, comparison of encoding techniques, FPGA design aspects and test results.

Design of current mirror integration ROIC for snapshot mode operation

Current mirror integration (CMI) read out integrated circuit (ROIC) topology provides a low input impedance to photo-detectors and provides large injection efficiency, large charge handling capacity and snapshot mode operation without in-pixel opamps. The ROIC described in this paper has been implemented with a modified current mirror circuit, with matched PMOS pairs for detector input stage and its biasing. The readout circuit has been designed for 30 × 30 μm2 pixel size, 4 × 4 array size, variable frame rate, 5 Mega pixel per second (Mpps). Experimental performance of the test chip has achieved 15 Me charge handling capacity, a high dynamic range of 83 dB, 99.8% linearity and 99.96% injection efficiency. The ROIC design has been fabricated in 3.3 V 1P6M UMC 180 nm CMOS process and tested up to 5 MHz pixel rate at room and at cryogenic temperature.

An all digital delay lock loop architecture for high precision timing generator

Remote sensing satellites use Charge Coupled Detectors (CCD) to achieve lower noise and higher dynamic range. Operation of a CCD requires high precision clocks/sequences. Generally it is achieved by using Phase Locked loop (PLL) or Delay Lock Loop (DLL). DLL are preferred for their low noise. An All Digital Delay Lock Loop (ADDLL) is designed to be used in the timing generation core. It is implemented using RTL design flow. This paper discusses design and implementation of an All Digital Delay lock loop suitable for implementation using RTL design methodology. It shows detailed blocks and implementation. It also discusses the challenges faced and their solutions in using RTL design for implementing this DLL. The resolution achieved was 620 ps in 180nm technology with phase error of 232 ps.

Bipolar voltage level shifter

Most of the advanced CCD sensors require bipolar clocks with large voltage swings. Hence there is a need of voltage level shifter to translate TTL/CMOS compatible levels to bipolar voltage swings (up to 20V). The CMOS drivers have advantages of low power and high input impedance but its main challenge is to attain negative voltage swing. Hence different topologies have been studied to implement the bipolar CMOS voltage level shifter design to guarantee a wide bipolar voltage conversion range with limited static power and total energy consumption. This circuit is implemented in a high voltage CMOS process. Design simulations have been carried out for TTL/CMOS input signals and output is verified for operational frequencies up to 20MHz and voltage swings up to 20V for all process-voltage-temperature variations. Designed level shifter provides output with rise /fall time less than 2ns. This paper discusses the designed circuit and detailed simulation results.

Implementation of high performance Readout Integrated Circuit

The Readout Integrated Circuit (ROIC) consists of charge integration, charge to voltage conversion, Pixel voltage multiplexing, signal transfer and amplification stage. The control circuit manages all the sequential events from charge integration to amplification stage. The large dynamic range requirement is the most challenging aspect in modern CMOS process. The infrared (IR) detectors looks for the integration of large charge handling capacity more than 10Me̅, at the same time sensitive enough to detect signals just above the noise floor of better than 900e̅. The ROICs uses a capacitor along with active elements for signal integration and processing. The amount of charge collected is defined by the charge handling capacity and limited by the size of integrating capacitor. In addition to this, signal processing also requires multiple large capacitors, which lead to complex tradeoffs, as all these must fit within the pixel size dictated by the requirements of IR detectors. Detectors operate with relatively high bias voltage, which further complicates interface design and silicon process selection. This paper discusses design optimization and implementation of direct injection ROIC. The 4×4 array ROIC test chip has 10 Me̅ charge handling capacity , maximum pixel pitch of 30μm, snapshot mode of operation, variable integration time, 3 Mega pixels per second (Mpps) readout rate and readout noise of 350e̅ reported at ambient temperature for the first time.

Efficient implementation of high performance Read out Integrated Circuit

The Read out Integrated Circuit (ROIC) consists of charge integration, charge to voltage conversion, Pixel voltage multiplexing, signal transfer and amplification stages. The control circuit manages all the sequential events from charge integration to amplification stage. Design and optimization of ROIC for hybrid detectors has multidimensional challenges including requirement for long simulation time for specified 25 to 100 Hz frame rate. Normally useful simulation data starts after 3 frame time and minimum transient simulation required for the same is 10 ms for 100 Hz frame rate. The simulation time for each input condition is ~120 hours with traditional simulators. ROIC critical specifications i.e. charge handling capacity and linearity has to be checked before chip integration to Pad. The linearity check requirs at least six point simulation and lead to 1 month simulation time on state of the art servers. Fast spice simulator with set_sim_level 5 has been used for the first time and reduces simulation time to 230 hours on same machine for the linearity simulation of ROIC. Test chip 4×4 ROIC has been fabricated using UMC 180 nm CMOS process and experimental results matched within 0.4% variation w.r.t. fast spice simulation results.

Design of low power, low noise & miniaturized electronics for methane sensors for mars

Indias future science vision emphasizes planetary explorations for better understanding of the universe, finding new domains of material resources, energy, environmental systems and habitat. Mars has a special significance of having many similarities with Earth. Methane Sensor for Mars (MSM) is one of the significant payloads of Indias first mars mission. The prime objective of the proposed Methane (CH4) Sensor for Mars (MSM) is to measure concentration of methane in the Martian atmosphere. The sensor configurations were worked out keeping in mind the mission requirements for low weight & power, while ensuring all the performance goals are met. This paper presents the design and development of low power miniaturized Proximity electronics module for MSM. The key challenges in the design of Proximity front end electronics are very low noise precision bias generator, low noise current to voltage conversion and low noise digitizer prior to final data. Proximity electronics also performs the function of temperature control of detectors and etalons. The proposed Proximity electronics system is modular catering to two channels realized in a low power, weight & size tray package. Proximity Electronics is realized in less than 500g and consumes power <;4W.

Generic and programmable Timing Generator for CCD detectors

Charge Coupled Devices (CCD) detectors are frequently used in imaging payloads developed for different satellite applications like space based astronomy and earth observations. CCDs are being used for onboard/satellite applications as it provides lower noise and higher dynamic range than CMOS detectors. CCDs are available in various architectures hence design of Timing Generator is planned based on CCD requirements. This paper discusses design methodology for generic timing generator which is completely programmable and supports various CCD architectures. The aim of design is to provide flexibility in terms of number of different types of clocks, effective image area and readout features with respect to various CCD architectures. Different supported CCD architectures, overall clock requirements, required readout features are studied and design architecture is worked out. The RTL design of Timing Generator is done using VHDL and block level verification is done using Verilog. The design is targeted to Xilinx Virtex-6 LX FPGA.

Design of sample and hold for 16 bit 5 Ms/S pipeline analog to digital converter

This work presents the design and simulation of a low power CMOS Sample and Hold OTA for a 16bit, 5Ms/S pipelined ADC. The designing of high precision amplifiers is challenging in modern CMOS process. It drives ADC design methodology towards advance calibration approaches and compromised with low SNR. This paper deals with advance design techniques for High gain like triple cascode and achieves a DC gain of 132 dB and 68 MHz unity gain bandwidth with a phase margin of 88 degrees while driving the 16pf load of the first stage. Transient response of Charge Redistribution SHA shows settling accuracy of 15uV in 66 nanoseconds while consuming 20mW power. Switched capacitor CMFB has been implemented for the gain boosting amplifiers and main stage amplifier respectively. The design has been implemented in UMC 0.18μm technology. Design methodology for high gain and better settling performance at low power are also discussed in detail.

Development of vertically stacked packaging based miniaturized camera electronics for high resolution imaging payloads

Future Remote Sensing Satellites with high resolution electro-optical payloads require multiple detectors to meet mission goals of multiple spectral bands and large swath. High speed detectors are available with limited pixels array length with multiple video ports. Large number of detectors at the focal plane calls for miniaturized camera electronics. Miniaturization requires usage of low power, low weight components and adaption of new packaging techniques like Multi chip module, System-in Package, Systems-on-chip and wafer level packaging etc. These technologies require multiple dice which are not readily available in required high quality levels. Hence, new packaging approach named as vertically stacked packaging (VSP) is developed in-house and demonstrated. This incorporates vertical stacking of PCBs, inter-board interfaces using copper leads, usage of flexi-rigid boards, single external interface connector and vertical passive component mounting. Here, using VSP technology, reduction is achieved in size by about 91% and weight by about 85% as compared to traditional packaging approaches. This paper mainly discusses the VSP development, optimization and integrated test results with 4K TDI detector.