Sandip Paul

AWiFS camera for resourcesat

Remote sensors were developed and used extensively world over using aircraft and space platforms. India has developed and launched many sensors into space to survey natural resources. The AWiFS is one such Camera, launched onboard Resourcesat-1 satellite by ISRO in 2003. It is a medium resolution camera with 5-day revisit designed for studies related to forestry, vegetation, soil, snow and disaster warning. The camera provides 56m (nadir) resolution from 817 km altitude in three visible bands and one SWIR band. This paper deals with configuration features of AWiFS Camera of Resourcesat-1, its onboard performance and also the highlights of Camera being developed for Resourcesat-2. The AWiFS is realized with two identical cameras viz. AWiFS-A and AWiFS-B, which cover the large field of view of 48°. Each camera consists of independent collecting optics and associated 6000 element detectors and electronics catering to 4 bands. The visible bands use linear Silicon CCDs, with 10μ × 7μ element while SWIR band uses 13μ staggered InGaAs linear active pixels. Camera Electronics are custom designed for each detector based on detector and system requirements. The camera covers the total dynamic range up to 100% albedo with a single gain setting and 12-bit digitization of which 10 MSBs are transmitted. The Camera saturation radiance of each band can also be selected through telecommand. The Camera provides very high SNR of about 700 near saturation. The camera components are housed in specially designed Invar structures. The AWiFS Camera onboard Resourcesat-1 is providing excellent imageries and the data is routinely used world over. AWiFS for Resourcesat-2 is being developed with overall performance specifications remaining same. The Camera electronics is miniaturized with reductions in hardware packages, size and weight to one third.

Design of high precision electronics for laser range finder

Resolution of Time to Digital Convertor (TDC) is a critical parameter in determining the overall performance of Time Of Flight based laser range finder system. This paper focuses on designing a high resolution Laser Range Finder (LRF) using Commercial-Off-The-Shelf (COTS) components. The designed LRF consists of a high resolution Time to Digital Convertor using Virtex-4 FPGA, Parallel to USB converter, High Voltage Power Supply and Data acquisition and display module. TDC generates START pulse at pulse repetition frequency (prf). This pulse is fed as trigger to laser TX. Avalanche Photo-Diode (APD) receiver with high voltage bias (~140V) generates a STOP pulse on receipt of reflected laser beam. This pulse is level translated and fed to TDC as STOP pulse. Digital Clock Manager (DCM) is used to achieve clock interpolation for improving resolution beyond 1 clock period. The output of TDC is parallel 16-bit digital count which is converted to serial USB protocol and interfaced to PC based data acquisition system. The raw data is processed and distance information is derived after calibration with known distance sets. Graphical User Interface (GUI) is developed for display, record and calibration. Full system resolution of about 22 cm is achieved in hardware for a range of 10m. The system has a power consumption of 6.15W.

Indigenous development of SERDES interface for miniaturization

In satellite systems, large amount of high speed data is required to be transmitted from one system to another. Conventional parallel data transmission requires a large number of cables/interface-packages and results in large weight and volume. Parallel interface in a typical future camera system requires >8000 cables between camera electronics and data handling system. In addition, with increase in transmission rate, problems associated with crosstalk become more critical. One possible solution identified is serial interface, also termed as SERDES (Serializer/DESerializer) interface. A typical SERDES interface comprises of encoder/decoder, PLL, timing-control and multiplexer/de-multiplexer. Encoding of serial data solves high speed serial data transmission problems by incorporating clock embedding, DC balancing, sync info insertion and error detection. DC balancing also solves the issue of Inter-Symbol Interference (ISI). Available SERDES interface devices have limitations like poor reduction factor, no clock embedding or non-availability of space qualified part. Hence, an attempt is made to understand and implement this interface with a goal of indigenous SERDES ASIC development, which will also overcome the above issues. Various serial encoding techniques are surveyed and 8B/10B encoding technique is finalized for very high speed serial data transmission. As an initial step, 8B/10B encoding based SERDES interface is implemented in a FPGA. Final serial data rate achieved is 250Mbps, which corresponds to transmission of 8-bit at 25MSPS and reduces interfaces by a factor of 8. Higher factors will be achieved by design with new encoding techniques like 12B/14B. This paper discusses different SERDES interfaces, comparison of encoding techniques, FPGA design aspects and test results.

Implementation of high performance Readout Integrated Circuit

The Readout Integrated Circuit (ROIC) consists of charge integration, charge to voltage conversion, Pixel voltage multiplexing, signal transfer and amplification stage. The control circuit manages all the sequential events from charge integration to amplification stage. The large dynamic range requirement is the most challenging aspect in modern CMOS process. The infrared (IR) detectors looks for the integration of large charge handling capacity more than 10Me̅, at the same time sensitive enough to detect signals just above the noise floor of better than 900e̅. The ROICs uses a capacitor along with active elements for signal integration and processing. The amount of charge collected is defined by the charge handling capacity and limited by the size of integrating capacitor. In addition to this, signal processing also requires multiple large capacitors, which lead to complex tradeoffs, as all these must fit within the pixel size dictated by the requirements of IR detectors. Detectors operate with relatively high bias voltage, which further complicates interface design and silicon process selection. This paper discusses design optimization and implementation of direct injection ROIC. The 4×4 array ROIC test chip has 10 Me̅ charge handling capacity , maximum pixel pitch of 30μm, snapshot mode of operation, variable integration time, 3 Mega pixels per second (Mpps) readout rate and readout noise of 350e̅ reported at ambient temperature for the first time.

Efficient implementation of high performance Read out Integrated Circuit

The Read out Integrated Circuit (ROIC) consists of charge integration, charge to voltage conversion, Pixel voltage multiplexing, signal transfer and amplification stages. The control circuit manages all the sequential events from charge integration to amplification stage. Design and optimization of ROIC for hybrid detectors has multidimensional challenges including requirement for long simulation time for specified 25 to 100 Hz frame rate. Normally useful simulation data starts after 3 frame time and minimum transient simulation required for the same is 10 ms for 100 Hz frame rate. The simulation time for each input condition is ~120 hours with traditional simulators. ROIC critical specifications i.e. charge handling capacity and linearity has to be checked before chip integration to Pad. The linearity check requirs at least six point simulation and lead to 1 month simulation time on state of the art servers. Fast spice simulator with set_sim_level 5 has been used for the first time and reduces simulation time to 230 hours on same machine for the linearity simulation of ROIC. Test chip 4×4 ROIC has been fabricated using UMC 180 nm CMOS process and experimental results matched within 0.4% variation w.r.t. fast spice simulation results.

Design of low power, low noise & miniaturized electronics for methane sensors for mars

Indias future science vision emphasizes planetary explorations for better understanding of the universe, finding new domains of material resources, energy, environmental systems and habitat. Mars has a special significance of having many similarities with Earth. Methane Sensor for Mars (MSM) is one of the significant payloads of Indias first mars mission. The prime objective of the proposed Methane (CH4) Sensor for Mars (MSM) is to measure concentration of methane in the Martian atmosphere. The sensor configurations were worked out keeping in mind the mission requirements for low weight & power, while ensuring all the performance goals are met. This paper presents the design and development of low power miniaturized Proximity electronics module for MSM. The key challenges in the design of Proximity front end electronics are very low noise precision bias generator, low noise current to voltage conversion and low noise digitizer prior to final data. Proximity electronics also performs the function of temperature control of detectors and etalons. The proposed Proximity electronics system is modular catering to two channels realized in a low power, weight & size tray package. Proximity Electronics is realized in less than 500g and consumes power <;4W.

3D packaged camera head for space use

Miniaturization is an essential requirement for development of space-borne electronics hardware. Recently, advancements in the device and packaging technology such as Analog Front End (AFE), FPGA and ASIC has enabled on-board designers to develop space worthy, high reliability miniaturized hardware meeting the functional and performance requirements. HMC, SIP, 3D packaging technology etc. can further miniaturize the hardware by embedding dice, devices, active and passive components. 3D packaging technology, which is ESA qualified, allows us to integrate packaged devices and printed circuit boards (PCB) with high reliability vertical interconnections. It is possible to migrate from existing PCB designs along with the same bill of material to 3D packaging technology. A development of miniaturized camera module consisting of 4K elements linear detector, detector drive electronics, analog video processing and digitizing electronics, timing and control logic along with serial data output has been carried out for space use using 3D packaging. Brief details of this camera hardware, development steps and realization challenges along with test results are given in this paper.

Development of vertically stacked packaging based miniaturized camera electronics for high resolution imaging payloads

Future Remote Sensing Satellites with high resolution electro-optical payloads require multiple detectors to meet mission goals of multiple spectral bands and large swath. High speed detectors are available with limited pixels array length with multiple video ports. Large number of detectors at the focal plane calls for miniaturized camera electronics. Miniaturization requires usage of low power, low weight components and adaption of new packaging techniques like Multi chip module, System-in Package, Systems-on-chip and wafer level packaging etc. These technologies require multiple dice which are not readily available in required high quality levels. Hence, new packaging approach named as vertically stacked packaging (VSP) is developed in-house and demonstrated. This incorporates vertical stacking of PCBs, inter-board interfaces using copper leads, usage of flexi-rigid boards, single external interface connector and vertical passive component mounting. Here, using VSP technology, reduction is achieved in size by about 91% and weight by about 85% as compared to traditional packaging approaches. This paper mainly discusses the VSP development, optimization and integrated test results with 4K TDI detector.

LISS-4 camera for resourcesat

The Indian Remote Sensing Satellites use indigenously developed high resolution cameras for generating data related to vegetation, landform /geomorphic and geological boundaries. This data from this camera is used for working out maps at 1:12500 scale for national level policy development for town planning, vegetation etc. The LISS-4 Camera was launched onboard Resourcesat-1 satellite by ISRO in 2003. LISS-4 is a high-resolution multi-spectral camera with three spectral bands and having a resolution of 5.8m and swath of 23Km from 817 Km altitude. The panchromatic mode provides a swath of 70Km and 5-day revisit. This paper briefly discusses the configuration of LISS-4 Camera of Resourcesat-1, its onboard performance and also the changes in the Camera being developed for Resourcesat-2. LISS-4 camera images the earth in push-broom mode. It is designed around a three mirror un-obscured telescope, three linear 12-K CCDs and associated electronics for each band. Three spectral bands are realized by splitting the focal plane in along track direction using an isosceles prism. High-speed Camera Electronics is designed for each detector with 12- bit digitization and digital double sampling of video. Seven bit data selected from 10 MSBs data by Telecommand is transmitted. The total dynamic range of the sensor covers up to 100% albedo. The camera structure has heritage of IRS- 1C/D. The optical elements are precisely glued to specially designed flexure mounts. The camera is assembled onto a rotating deck on spacecraft to facilitate ± 26° steering in Pitch-Yaw plane. The camera is held on spacecraft in a stowed condition before deployment. The excellent imageries from LISS-4 Camera onboard Resourcesat-1 are routinely used worldwide. Such second Camera is being developed for Resourcesat-2 launch in 2007 with similar performance. The Camera electronics is optimized and miniaturized. The size and weight are reduced to one third and the power to half of the values in Resourcesat-1.