Arup Roy Chowdhury

SW-MW infrared spectrometer for lunar mission

SW-MW Imaging Infrared Spectrometer, the Hyperspectral optical imaging instrument is envisaged to map geomorphology and mineralogy of lunar surface. The instrument is designed to image the electro-magnetic energy emanating from moon’s surface with high spectral and spatial resolution for the mission duration from an altitude of 100 km. It is designed to cover 0.8 to 5 μm in 250 spectral bands with GSD 80m and swath 20km. Primarily, there are three basic optical segments in the spectrometer. They are fore optics, dispersing element and focusing elements. The payload is designed around a custom developed multi-blaze convex grating optimized for system throughput. The considerations for optimization are lunar radiation, instrument background, optical throughput, and detector sensitivity. HgCdTe (cooled using a rotary stirling cooler) based detector array (500x256 elements, 30μm) is being custom developed for the spectrometer. Stray light background flux is minimized using a multi-band filter cooled to cryogenic temperature. Mechanical system realization is being performed considering requirements such as structural, opto-mechanical, thermal, and alignment. The entire EOM is planned to be maintained at ~240K to reduce and control instrument background. Al based mirror, grating, and EOM housing is being developed to maintain structural requirements along with opto- mechanical and thermal. Multi-tier radiative isolation and multi-stage radiative cooling approach is selected for maintaining the EOM temperature. EOM along with precision electronics packages are planned to be placed on the outer and inner side of Anti-sun side (ASS) deck. Power and Cooler drive electronics packages are planned to be placed on bottom side of ASS panel. Cooler drive electronics is being custom developed to maintain the detector temperature within 100mK during the imaging phase. Low noise detector electronics development is critical for maintaining the NETD requirements at different target temperatures. Subsequent segments of the paper bring out system design aspects and trade-off analyses.

Design of current mirror integration ROIC for snapshot mode operation

Current mirror integration (CMI) read out integrated circuit (ROIC) topology provides a low input impedance to photo-detectors and provides large injection efficiency, large charge handling capacity and snapshot mode operation without in-pixel opamps. The ROIC described in this paper has been implemented with a modified current mirror circuit, with matched PMOS pairs for detector input stage and its biasing. The readout circuit has been designed for 30 × 30 μm2 pixel size, 4 × 4 array size, variable frame rate, 5 Mega pixel per second (Mpps). Experimental performance of the test chip has achieved 15 Me charge handling capacity, a high dynamic range of 83 dB, 99.8% linearity and 99.96% injection efficiency. The ROIC design has been fabricated in 3.3 V 1P6M UMC 180 nm CMOS process and tested up to 5 MHz pixel rate at room and at cryogenic temperature.

An all digital delay lock loop architecture for high precision timing generator

Remote sensing satellites use Charge Coupled Detectors (CCD) to achieve lower noise and higher dynamic range. Operation of a CCD requires high precision clocks/sequences. Generally it is achieved by using Phase Locked loop (PLL) or Delay Lock Loop (DLL). DLL are preferred for their low noise. An All Digital Delay Lock Loop (ADDLL) is designed to be used in the timing generation core. It is implemented using RTL design flow. This paper discusses design and implementation of an All Digital Delay lock loop suitable for implementation using RTL design methodology. It shows detailed blocks and implementation. It also discusses the challenges faced and their solutions in using RTL design for implementing this DLL. The resolution achieved was 620 ps in 180nm technology with phase error of 232 ps.

Implementation of high performance Readout Integrated Circuit

The Readout Integrated Circuit (ROIC) consists of charge integration, charge to voltage conversion, Pixel voltage multiplexing, signal transfer and amplification stage. The control circuit manages all the sequential events from charge integration to amplification stage. The large dynamic range requirement is the most challenging aspect in modern CMOS process. The infrared (IR) detectors looks for the integration of large charge handling capacity more than 10Me̅, at the same time sensitive enough to detect signals just above the noise floor of better than 900e̅. The ROICs uses a capacitor along with active elements for signal integration and processing. The amount of charge collected is defined by the charge handling capacity and limited by the size of integrating capacitor. In addition to this, signal processing also requires multiple large capacitors, which lead to complex tradeoffs, as all these must fit within the pixel size dictated by the requirements of IR detectors. Detectors operate with relatively high bias voltage, which further complicates interface design and silicon process selection. This paper discusses design optimization and implementation of direct injection ROIC. The 4×4 array ROIC test chip has 10 Me̅ charge handling capacity , maximum pixel pitch of 30μm, snapshot mode of operation, variable integration time, 3 Mega pixels per second (Mpps) readout rate and readout noise of 350e̅ reported at ambient temperature for the first time.

Design of low power, low noise & miniaturized electronics for methane sensors for mars

Indias future science vision emphasizes planetary explorations for better understanding of the universe, finding new domains of material resources, energy, environmental systems and habitat. Mars has a special significance of having many similarities with Earth. Methane Sensor for Mars (MSM) is one of the significant payloads of Indias first mars mission. The prime objective of the proposed Methane (CH4) Sensor for Mars (MSM) is to measure concentration of methane in the Martian atmosphere. The sensor configurations were worked out keeping in mind the mission requirements for low weight & power, while ensuring all the performance goals are met. This paper presents the design and development of low power miniaturized Proximity electronics module for MSM. The key challenges in the design of Proximity front end electronics are very low noise precision bias generator, low noise current to voltage conversion and low noise digitizer prior to final data. Proximity electronics also performs the function of temperature control of detectors and etalons. The proposed Proximity electronics system is modular catering to two channels realized in a low power, weight & size tray package. Proximity Electronics is realized in less than 500g and consumes power <;4W.

Generic and programmable Timing Generator for CCD detectors

Charge Coupled Devices (CCD) detectors are frequently used in imaging payloads developed for different satellite applications like space based astronomy and earth observations. CCDs are being used for onboard/satellite applications as it provides lower noise and higher dynamic range than CMOS detectors. CCDs are available in various architectures hence design of Timing Generator is planned based on CCD requirements. This paper discusses design methodology for generic timing generator which is completely programmable and supports various CCD architectures. The aim of design is to provide flexibility in terms of number of different types of clocks, effective image area and readout features with respect to various CCD architectures. Different supported CCD architectures, overall clock requirements, required readout features are studied and design architecture is worked out. The RTL design of Timing Generator is done using VHDL and block level verification is done using Verilog. The design is targeted to Xilinx Virtex-6 LX FPGA.

Design of sample and hold for 16 bit 5 Ms/S pipeline analog to digital converter

This work presents the design and simulation of a low power CMOS Sample and Hold OTA for a 16bit, 5Ms/S pipelined ADC. The designing of high precision amplifiers is challenging in modern CMOS process. It drives ADC design methodology towards advance calibration approaches and compromised with low SNR. This paper deals with advance design techniques for High gain like triple cascode and achieves a DC gain of 132 dB and 68 MHz unity gain bandwidth with a phase margin of 88 degrees while driving the 16pf load of the first stage. Transient response of Charge Redistribution SHA shows settling accuracy of 15uV in 66 nanoseconds while consuming 20mW power. Switched capacitor CMFB has been implemented for the gain boosting amplifiers and main stage amplifier respectively. The design has been implemented in UMC 0.18μm technology. Design methodology for high gain and better settling performance at low power are also discussed in detail.