Ram Kelkar

Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and /spl plusmn/50 ps jitter

Phase-locked loops (PLL) are widely used for clock-phase synchronization, frequency synthesis and clock distribution. It is highly desirable that the standard digital CMOS process be used in the PLL design because process modifications increase product cost. Other desirable features include insensitivity to noise and a fully integrated design. The PLL design reported in this paper has all the above features. A standard digital CMOS process is used to produce a fully differential structure that is immune to substrate and supply noise. The PLL function includes multiplication of frequency and synchronization of input and output clock phases. The architecture is unique because resistors are not needed for PLL loop stabilization.

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

As exemplified by standards such as OIF CEI-25G, 32G-FC, and next-generation 100GbE, serial link data rates are being pushed up to 25 to 28Gb/s in order to increase I/O system bandwidth. Such speeds represent a near doubling of the state-of-the-art for fully integrated transceivers [1-3]. With scaling no longer providing large gains in device speed, significant design advances must be made to attain these data rates. This paper describes a 28Gb/s serial link transceiver featuring a source-series terminated (SST) driver topology with twice the speed of existing designs, a two-stage peaking amplifier with capacitively-coupled parallel input stages and active feedback, and a 15-tap DFE. The use of capacitive level-shifters allows a single current-integrating summer to drive the parallel paths used for speculating the first two DFE taps.

A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications

This paper describes a wide-range programmable frequency synthesizer building block for 4.25Gbps serial link applications. A unique feature of the design is the use of variable gain charge pumps to adjust loop gain as well as damping in order to minimize output jitter. The synthesizer architecture includes pre and post dividers to maximize programmability. A novel implementation of the high speed divide circuit is also described