Stephen D. Wyatt

Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and /spl plusmn/50 ps jitter

Phase-locked loops (PLL) are widely used for clock-phase synchronization, frequency synthesis and clock distribution. It is highly desirable that the standard digital CMOS process be used in the PLL design because process modifications increase product cost. Other desirable features include insensitivity to noise and a fully integrated design. The PLL design reported in this paper has all the above features. A standard digital CMOS process is used to produce a fully differential structure that is immune to substrate and supply noise. The PLL function includes multiplication of frequency and synchronization of input and output clock phases. The architecture is unique because resistors are not needed for PLL loop stabilization.

Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration

In this paper, a new adaptive PLL is implemented. This PLL employs a simple yet effective jitter test circuit to monitor the PLL jitter performance. Additionally, it uses a digital control unit to dynamically adjust the switched loop filter to suppress the jitter. By using this structure, the trade-off between the PLL locking speed and jitter performance can be balanced