Anjali R. Malladi

Testing methods for integrated circuit of phase locked loops

The conventional integrated circuit phase locked loop (PLL) has few output signals and offers limited testability. In an event where PLL function does not conform to the specifications, it is often hard and time consuming to debug the problems due to limited accessibility of the internal signals. In this paper we propose a testing structure which uses the existing PLL blocks with minimal additional circuitry thus minimizing the area penalty. The VCO (voltage controlled oscillator) frequency range, VCO gain curve, divider operating range and noise contribution can be determined using the proposed method.

A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications

This paper describes a wide-range programmable frequency synthesizer building block for 4.25Gbps serial link applications. A unique feature of the design is the use of variable gain charge pumps to adjust loop gain as well as damping in order to minimize output jitter. The synthesizer architecture includes pre and post dividers to maximize programmability. A novel implementation of the high speed divide circuit is also described