Sarasvathi Thangaraju

Novel stress-free Keep Out Zone process development for via middle TSV in 20nm planar CMOS technology

For the first time, a near-Zero Keep Out Zone TSV capability is demonstrated utilizing the Middle Of Line (MoL) layer stack process development and optimization. This is MoL layer stack consisted of a nitride, PMD oxide, and contact protection layer. Careful selection of a high CTE Contact Protection layer to compensate the TSV induced stress in Silicon (Silicon CTE is 2.3 ppm/°C) yields the near-Zero Keep Out Zone, confirmed with silicon measurement data.

Successful void free gap fill of 3µm, high AR via middle, Through Silicon Vias at wafer level

This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, Through Silicon Vias (TSV), of 3μm top entrant critical dimension (CD) and 50μm depth. Higher AR TSV integration is explored due to the lower stress influence of TSVs observed in adjacent CMOS devices.

Challenges to via middle TSV integration at sub-28nm nodes

This work presents the via middle TSV integration at sub-28 nm nodes using a new local interconnect scheme involving V0 vias. Various V0 schemes are presented along with their respective resistance, capacitance and leakage current data. The characterization and reliability results are presented through TSV daisy chain structures and MOL via chains.

New interferometric measurement technique for small diameter TSV

High aspect ratio through silicon vias (TSV) present a challenge for measurement of bottom critical dimension (BCD) and depth. TSVs smaller than 5 micron diameter with greater than 12:1 depth to BCD aspect ratio have particularly poor signal to noise ratio in the measured signal. This paper proposes a method for improving the interferometric measurement of these very small and high-aspect ratio TSVs with data showing the feasibility of measuring both BCD and depth of 19:1 aspect ratio TSVs. This work demonstrates the capability to analyze the scanning white-light interferometry (SWLI) signal for such high aspect ratio TSV BCD and depth measurements with >0.95 R2 correlation to reference metrology obtained through cross section SEM. Precision of within 2.5% of nominal BCD and within 0.1% of nominal depth was demonstrated for 10x repeatability measurements.

Correlation study of white light interferometer measurements with atomic force microscope measurements for post-CMP dishing measurements applied to TSV processing

White light interferometry (WLI) has been used in the semiconductor industry for the measurement of topography, step height, and via depth, utilizing its fundamentally short coherence length. This allows the tool to achieve nanometer level resolution, making this technique ideal for through silicon via (TSV) measurements for high aspect ratio vias. In this paper, we will discuss one of the important measurement steps within 20 nm/14 nm technology node TSV processing, and how WLI is applied to make the measurements. For the post-chemical mechanical polish (CMP) dishing measurement near TSVs, we have evaluated a wafer map for processing that includes the wafer center and edge area. The CMP dishing measurement can be broken into two distinct regions of measurement: 1) Within-Field dishing and 2) Within-TSV dishing. Greater than 90% correlation with an AFM measurement for all dishing measurement regions has been observed. Less than 0.5% deviation for repeatability data pertaining to this measurement has also been observed.

Metrology of white light interferometer for TSV processing

3D integration technology offers an alternative to traditional packaging designs. In traditional Moore’s law scaling, features are added to the die, with graphics, memory control and logic coprocessors all integrated onto the silicon chip. TSV (through silicon via) processing utilizes vertical electrical interconnects that provide the shortest possible path to establish an electrical connection from the device side to the backside of a die. This indirectly allows continues “Moore”- like scaling while only affecting the device packaging. White light interferometry (WLI) has been used for the measurement of topography, step height and via depth using its short coherence length. The nanometer level resolution of this technique is ideal for TSV measurements in the high aspect ratio vias. In this work, six white light interferometer measurements for TSV processing are discussed along with the importance of these measurements to TSV processing, namely: 1. Post-TSV etch: depth, top CD (TCD) and bottom CD (BCD) 2. Post-TSV liner BCD 3. Post-TSV barrier seed BCD 4. TSV electro-chemically plated (ECP) copper bump step height 5. Post-annealing bump step height 6. TSV CMP dishing These measurement steps have been implemented in-line for advanced technology node TSV process flows at GLOBALFOUNDRIES. The measurements demonstrate 90% correlation to reference metrology and <0.5% repeatability. Cross section SEM was used as a reference for TSV profile and Cu bump measurements while AFM was used as a reference for dishing measurements.