Ramakrishna K. Tanikella

Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies

Structures and methods for avoiding hold time violations in a programmable logic device

Integrated circuit interconnect structure having reduced coupling between interconnect lines

Six-input look-up table and associated memory control circuitry for use in a field programmable gate array

Structures and methods of testing interconnect structures in programmable logic devices

Six-input look-up table for use in a field programmable gate array

Methods of initializing routing structures in integrated circuits

Reduction of single event upsets within a semiconductor integrated circuit

Single event upset enhanced architecture

PROGRAMMABLE INTEGRATED CIRCUIT WITH MIRRORED INTERCONNECT STRUCTURE