Ramana Murthy

TSV Cu Filling Failure Modes and Mechanisms Causing the Failures

In this paper, we report through-silicon via (TSV) Cu filling failure modes and categorize them into three major regions based on their causes. First, Si etch-related region for the TSV defining. Si etch defects, such as bottom corner notch, Si grass at the bottom, surface roughness, and sponge-like defect, cause Cu seed layer loss at the defect areas. It causes electrical disconnection resulting in the TSV Cu filling failure. Second, Cu seed layer-related region. Defects include poor Cu seed layer step coverage and oxidation of the Cu seed layer from the Cu seed layer deposition until the TSV Cu electroplating from the Cu seed layer deposition. They result in aggrandizing terminal effect, which makes Cu ion reduction at the TSV bottom difficult. Third, Cu electroplating-related region. The most important factor in this region is chemical concentration control because the TSV Cu filling by bottom up filling mainly depends on the cooperation of three additives of suppressor, accelerator, and leveler. Another important factor in the region is current density ramp up rate. It is critical to ramp up the current density with an appropriate rate to prevent pinchoff plating causing voids inside the TSVs. These regions are closely connected with each other and the relationship needs to be understood to overcome the TSV Cu filling failure.

Polysilicon interconnections (FEOL): Fabrication and characterization

Three dimensional silicon integration technologies are gaining considerable attention as the traditional CMOS scaling becoming more challenging and less beneficial. The advanced packaging solutions based on thin silicon carrier are being developed to interconnect integrated circuits and other devices at high densities. A key enabling technology element of the silicon carrier is Through Silicon Via (TSV), which can provide vertical interconnects in stacked ICs. In this paper, we present vias-first process to realize vertical interconnects that is fully FEOL compatible. The vias are filled by doped polysilicon and wafers with such pre-fabricated vias can be used as the starting wafers for any CMOS device processing. The process details and their characterization are elaborated along with the physical and electrical analysis of such vias.

Impact of packaging design on reliability of large die Cu/low-κ (BD) interconnect

This paper presents the study on the effect of low k stacked layer, chip pad design structures, and shift pad design TM of a large die size Cu/low kappa (BDtrade) chip for improving assembly and reliability performance on organic buildup substrate FCBGA (FlipChip ball grid array). Bump shear characterization has been performed on the integrity of different stacked layer and pad structure, supported by bump shear modeling analysis. Initial reliability testing was performed on assembled package to identify the best choice of design and finally implemented on the reliability test vehicle for verification. In addition, a potential chip crack problem due to excessive warpage in FCBGA with large die assembly is examined and a simple failure criterion is proposed.

Relationship Between Wafer-Level Warpage and Cu Overburden Thickness Controlled by Isotropic Wet Etching for Through Si Vias

In this paper, we developed an isotropic wet etching process in a capsule-type bevel etch chamber to reduce a Cu overburden of through Si via (TSV) for less wafer-level warpage with 300 mm wafers. We report the relationship between the wafer-level warpage and the Cu overburden thicknesses controlled by the isotropic wet etching with diluted solution of hydrogen peroxide and sulfuric acid, which is widely used for Cu wet etching. After Cu filling by electroplating, there are humps at the top of the TSVs; therefore, the isotropic wet etching can be considered as a solution to etch away the Cu overburden without any damages on the TSVs. We modified the capsule-type bevel etch chamber to avoid serious attack on TSVs at the center area of the wafer caused by the etchant delivery path. We also adjusted the process parameters to have a controllable Cu etch rate. The etch rate of ~ 0.2 μm/s and the uniformity of ~ 3% were achieved. The overburden was able to be etched up to 3 μm m from the initial Cu overburden. While the Cu overburden decreased during the isotropic wet etching, the TSVs were protected from the etchant because of the humps at the top of the TSVs. After the Cu electroplating, there was a grain size difference between the Cu at TSV and the Cu at field area. Because the microstructural difference caused a galvanic corrosion during the wet etching, the etch rate of the adjacent Cu around TSV was faster than the Cu at any other area. That resulted in exposure of dielectric layer at the adjacent area around TSVs when the Cu overburden was etched heavily. It may be another protection mechanism of TSV during the isotropic wet etching. The wafer-level warpage of the wafer with the Cu overburden etched up to 3 μm after the annealing decreased by 50% from that of the wafer with the initial Cu overburden. The wafer-level warpage exhibited a linear relationship with the Cu overburden thickness controlled by the isotropic wet etching.

Impact of Packaging Design on Reliability of Large Die Cu/Low-

This paper presents the study on the effect of low-κ stacked layer, chip pad design structures, and shift pad design of a large die size Cu/low-κ chip for improving assembly and reliability performance on organic buildup substrate flip chip ball grid array (FCBGA). Bump shear characterization has been performed on the integrity of different stacked layer and pad structure, supported by bump shear modeling analysis. Initial reliability testing was performed on assembled package to identify the best choice of design and finally implemented on the reliability test vehicle for verification. In addition, a potential chip crack problem due to excessive warpage in FCBGA with large die assembly is examined and a simple failure criterion is proposed.

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3D Through-silicon via (TSV) has been acknowledged as one of the future chip design technologies. In this paper, via last after Back End Of Line (BEOL) and before bonding, CMOS wafer with 18 layers of multilayer dielectric dry etching prior to deep silicon etching is presented. TSV Via dry etching of CMOS wafer of 40 um, 8.5 um thick multilayer dielectric which consists of several dielectric materials such as LOW K, SiCOH, Si3N4, HARP and USG will be discussed. Three masking schemes and their respective challenges are reported in the paper. Using 5.9 um photo resist and optimum etching recipe, we have demonstrated multilayer dielectric stack dry etching resulting in straight smooth via required by subsequent TSV etching into Si substrates.

(BD) Interconnect

During the fabrication of aluminum MEMS (Microelectromechanical Systems) structures for display applications, surface corrosion or pitting appeared intermittently on the aluminum structures after aluminum (Al) plasma etch and post etch cleaning. Such surface corrosion severely limited the light reflecting capabilities of the planar aluminum micromirrors. The formulated organic solvent cleaners or post etch residue removers used after aluminum plasma etch such as NE14 from Air Products (AP) and ST250 from Advanced Technologies and Materials Incorporated (ATMI) were suspected to be the main culprits of the Al corrosion but without conclusive evidences. In order to better understand the causes of the post etch aluminum corrosion, extensive work has been carried out to look at the factors that may lead to Al corrosion after plasma etch and post etch clean. In particular, we have evaluated the surfaces of Al structures after NE14 and ST250 post etch cleaning using tools such as SEM and AFM. We focused on the three main aspects that may affect the Al corrosion: The Al plasma etch process, the extended cleaning in the organic solvent chemistries, and the Al corrosion as a result of water dilution in the organic solvent cleaners.

TSV via-last: Optimization of multilayer dielectric stack etching

Various types of polyimide have been used widely in the manufacturing of integrated circuits and MEMS’ (Micro Electrical Mechanical Systems) such as sensors. These organic spin-on polymers exhibit a wide range of mechanical and electrical properties and have been commonly used for electrical insulation as well as device passivation and protection. In addition, these organic spin-on polymers serve as excellent sacrificial materials for forming cavities on MEMS structures. This work studies the gapfill properties of several polyimides after spin-coating and curing. In addition, this work examines and compares the gapfilling and planarization properties of a number of different polyimides, including multiple layers of polyimides for gapfilling and planarization.

Control of corrosion on aluminum MEMS structures after post etch clean

This paper reports a process of filling and planarization of microstructures for MEMS and wafer level packaging application. In this work, cavities of 5-10mm depth and 20-100mm in length/width are filled using multiple coatings of polyimide with kinematic viscosities in the range of 20-130St. Such filling results in overfilling of polyimide in the range of 2 to 10mm due to variation in density and geometry of microstructure. A chemical and mechanical polishing (CMP) based planarization process, to achieve polyimide thickness variation <0.2mm in varied structures is presented.

Gapfill Study of Polyimides for MEMS Applications

The step coverage of a Cu seed layer is one of critical factors to be controlled in order to achieve void-free TSV for 2.5D and 3D IC. The step coverage of a Cu seed layer can be changed by aging of the Cu seed layer with time and there are two mechanisms in its aging. The one was the oxidation of a Cu seed layer which can change the step coverage by changing the actual thickness of the Cu seed layer. The other was the self-annealing of a Cu seed layer which can change the step coverage by changing the electrical resistivity due to its grain growth. Both of them can result in higher terminal effect causing the failure of void-free TSV Cu filling.