Xiaomin Wei

A Touch Prediction and Window Sensing Strategy for Low-Power and Low-Cost Capacitive Multitouch Screen Systems

A new multitouch sensing strategy, named the Touch Prediction and Window Sensing (TPWS), is proposed and realized in this paper for projected capacitive touch screens. The detection procedures of TPWS are divided into two stages: a pre-sensing stage for predicting the possible touched regions, and a window sensing stage for obtaining the accurate touched positions. Since the measurements of the untouched sensing cells are reduced significantly, the TPWS strategy needs lower efforts on signal readout and data processing than the traditional strategies. A prototype system was designed and realized, which consists of three identical 48-channel readout chips, a 15-in capacitive touch screen, and a commercial host processor. The readout chip is specially designed for the TPWS strategy using 0.13 μm 1.8 V/5 V CMOS process. The measurement results show that, the total power consumption of the system is only about 65 mW with a power supply of 5 V, and the reporting rate of the system achieves 500 Hz for no touches and 83 Hz for ten touches. The area of the readout chip is only 0.087 mm2 per sensing channel. The proposed TPWS strategy can be used to realize low-power and low-cost multitouch screen system, and it is especially efficient for large-sized screen.

A DC-coupling area-efficiency readout circuit for CdZnTe detectors

In this paper, a DC-coupling readout circuit is presented in order to readout the signal from CdZnTe detectors. A differential stage is added in CSA to compensate the leakage current introduced by the CdZnTe crystal. A compact shaper is designed to achieve low area with wide range of adjustable peaking time from 3 μ s to 10 μ s. The area of proposed circuit is about 130 μ m × 1100 μ m. The experimental results show that the ENC is 70 e− + 14 e−/pF and the gain is about 152 mV/fC at the peaking time of 4 μ s.

A new differential measurement scheme for projected-capacitive touch controller

For sake of lightness, thinness and low cost, single-layer projected-capacitive touch panel is popular for electronic products. The interference from liquid crystal display in single-layer touch screens is more serious than that in two-layer touch screens. For touch controller IC, differential measurement, which provides high common mode noise rejection, can be used in this case in order to suppress the interference. However, the differential measurement is sensitive to the self-capacitance variation besides the mutual-capacitance variation. As a result, “ghost points” exist in multi-touch application. In order to distinguish the “ghost points”, a new differential measurement scheme is proposed in this paper. By applying complementary excitations on two adjacent drive electrodes, the new measurement scheme only responses to mutual-capacitance variation. A controller IC has been designed based on the proposed scheme in a 0.35 μm 5V CMOS process. The simulation results show that the new scheme effectively solved the problem of “ghost point”. In addition, perfect conversion linearity between mutual capacitance variation and the PGA output voltage is obtained. The touch controller IC in this paper is being fabricated, and the test results are expected in the near future.

Design of a 10-bit 1 MS/s pipelined SAR ADC for CZT-based imaging system

A 10-bit 1 MS/s pipelined SAR ADC for CZT-based imaging system is presented. The ADC is composed of three pipeline stages which are two 4-bit SAR-based Multiplying Digital Analog Converters (MDACs) and a 4-bit SAR ADC. In order to improve the performances of the proposed ADC, several techniques were proposed. Firstly, a novel 4-bit MDAC circuit which can eliminate the offset voltage of residue amplifier is proposed here. Secondly, digital correction technique is adopted for eliminating the error induced by offset voltage of comparator. As long as the offset voltage is less than 1/16 Vref, the offset voltage can be corrected. Thirdly, digital calibration technique is used to calibrate the gain errors due to capacitor mismatch, finite open-loop gain and finite gain band width (GBW) of residue amplifier and so on. The prototype chip was fabricated in a 0.35m CMOS process and occupies a core area of 9601260m2. The proposed pipleined SAR ADC achieves 55.6dB SNDR at 1MS/s sampling rate and consumes 8.2mW power. The FOM of the proposed ADC is 17.2pJ/conversion-step.

Methods for predicting dark-current distribution of CMOS image sensor in radiation environment

Nowadays, CMOS image sensors are more and more used in a wide variety of applications, especially in satellite systems, where they are exposed to space radiation environment. In-orbit sensors suffer from radiation induced dark-current degradation that the dark-current mean value and non-uniformity increase, which results in the signal-to-noise-ratio decrease affecting the image quality. Based on the principle of radiation effects on semiconductor devices, this paper analyzes the ionizing and displacement damage effects in CMOS image sensors due to γ-rays and protons radiation, and proposes a method for dark-current distribution modeling in the mixed radiation environment. Simulation results proves that the proposed method is well adapted to predict the dark-current distributions for a device which is exposed to both γ-rays and protons radiation at the same time.

A high-gain, third-order analogue signal processing ASIC for DC-coupled CdZnTe detectors

In order to read out the signal of CdZnTe detectors, this paper presents a high-gain, third-order analogue signal processing application specific integrated circuit (ASIC). The charge generated in detectors can be amplified and shaped by this circuit. Dual-stage charge sensitive amplifier and baseline holder are utilized to compensate the leakage current from DC-coupled detectors. A novel shaper is proposed to improve the output amplitude and achieve high gain. A high-order shaper in our previous work is also presented for comparison. The proposed ASIC has been designed and verified in a standard commercial 2P4M 0.35μm CMOS process. The die area of one channel is 975 μm × 142 μm. The gain is 185 mV/fC at the peaking time of 1 μs. The peaking time can be adjusted from 1 μs to 3 μs. The maximum leakage current of 5 nA can be compensated.

Design of a front-end signal processing circuitry for Capacitive Multi-touch Screens

Capacitive Multi-touch Screens are attractive for smart phone, tablet PC, industrial monitors, 3D or 4D visualization interactions, commercial office and so on. With the increasing size of the touch screen, a touch prediction and window sensing (TPWS) strategy was proposed for reducing the system costs and power consumptions. However, the traditional front-end signal processing circuits with charge integrating are not proper for the TPWS strategy. This paper presents a new front-end signal processing circuits dedicated for the TPWS touch screen systems. A charge to digital converter (CDC) is designed to realize the functions of charge integrating circuits and analog to digital converter (ADC) in the traditional touch screen system for the capacitance measurement. Combining differential input sensing and single input sensing, both the capacitance of an intersection and the shunt capacitance of the intersections on one electrode,that is required for the TPWS system, can be measured with the proposed circuits. The design was realized in a 0.13 μm 1.8 V/5 V CMOS process. The area of the prototype chip is 0.087 mm2 per sensing channel. The tests were performed with a 15-inch touch panel. The total power consumption of the system is only about 65 mW with power supply of 5 V, and the reporting rate of the system achieves 500 Hz for none touch and 83 Hz for 10 touches. The proposed circuits satisfy the requirements of the TPWS touch screen systems, and can also be used for the other capacitive touch screen systems.

Design of a 12-bit 2 MS/s 12 mW pipelined SAR ADC in CMOS 0.18 μm technology for CZT-based imaging system

This paper presents a 12-bit 2 MS/s pipelined successive approximation register (SAR) ADC for CZT-based imaging system. The proposed ADC is divided into a first-stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. The first-stage MDAC has a gain of 16 instead of the usual gain of 64, which considerably minimizes the power dissipation of residue amplifier. The second-stage 8-bit SAR ADC employs unit bridge capacitor split-capacitor architecture aiming to reduce the load capacitance of residue amplifier so as to minimize the power dissipation of the proposed ADC. Moreover, a code-randomized calibration algorithm is proposed to improve the linearity of the second-stage 8-bit split-capacitor SAR ADC. In addition, several radiation-hardened-by-design techniques are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 μ m mixed-signal 1.8 V/3.3 V process and occupied a core area of 0.71 mm2. The proposed pipelined SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 63.2 dB at 2 MS/s sampling rate and consumes 12 mW power in total. The figure of merit (FoM) of the proposed ADC is 5.06 pJ/conversion-step.

Design of a Touch Controller for Multitouch Screen System With Touch Prediction and Window Sensing (TPWS) Strategy

The touch prediction and window sensing (TPWS) strategy is an effective approach to realize low-cost and low-power multitouch screen systems, especially for large-sized touch screen panels. The structures of traditional touch controller using charge integrating amplifier is not suitable for the TPWS touch screen systems. This paper presents a new touch controller, which is designed for the TPWS touch screen systems and is emphasized to improve the SNR and reporting rate of system. The differential measurement scheme with a full driving method is proposed to eliminate the influences on the SNR and the reporting rate of system caused by the LCD noise, the charger noise and the signal transmission delay on Indium-Tin Oxide (ITO) electrodes. The designed touch controller is realized in a 0.13 µm 1.8 V/5 V embedded flash CMOS process with the chip size of 2.5 × 2.8 mm2. The test results demonstrate that this touch controller supports the TPWS strategy very well and its performances are improved significantly. Comparing with the previous design, the SNR is improved from 25 to 36 dB, and the reporting rate is increased from 83 to 120 Hz.

A radiation-hardened low-power pipelined SAR ADC for CZT-based imaging system

A 12-bit 2M Samples/s pipelined SAR ADC for CZT-based imaging system is presented. It pipelines a first stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second stage 8-bit SAR ADC. The inter-stage gain of 16 instead of 64 is implemented in the 6-bit SAR-based MDAC for minimizing the power dissipation. The second stage 8-bit SAR ADC uses a split-capacitor architecture for reducing the load capacitance of the residue amplifier and then the power dissipation is minimized. In addition, several radiation-hardened-by-design technologies are adopted at layout design for improving pipelined SAR ADCs radiation tolerance. The prototype chip was fabricated in 0.18 μm mixed-signal 1.8V/3.3V process and occupies a core area of 700μm × 1018 μm. The proposed pipelined SAR ADC achieves 63.7 dB SNDR at 2M Samples/s sampling rate and consumes 12 mW power. The FOM of the proposed ADC is 4.76pJ/conversion-step.