Randy Mckee

SRAM Cell Static Noise Margin and VMIN Sensitivity to Transistor Degradation

The SRAM cell sensitivity to transistor degradation is understood using a novel test methodology. A new, semi-empirical model that captures the observed trends is derived. The key findings include (a) cell sensitivity to NBTI degradation is high when low NMOS VT/ high PMOS VT combination arises (b) NBTI contribution to product VMIN drift arises mainly from the mean VTP shift which moves the overall distribution, and (c) NBTI-induced variance is overwhelmed by the time-zero variation of the six transistors of the SRAM. These findings enable a quantitative prediction that the NBTI-induced VMIN increase during burn-in is of the order of the NBTI-induced VT shift

A Screening Methodology for VMIN Drift in SRAM Arrays with Application to Sub-65nm Nodes

SRAMs are an integral part of system on chip devices. With transistor and gate length scaling to 65nm/45nm nodes, SRAM stability across the products lifetime has become a challenge. Negative bias temperature instability, defects, or other phenomena that may manifest itself as a transistor threshold voltage (VT) increase can result in VMIN drift of SRAM memory cells through burn-in and/or operation. A direct assessment at time-zero is difficult because the transistor VT has not yet shifted, and therefore no capability to screen VMIN shift at time zero can be developed. This work describes a methodology developed on 65nm low power and high performance process technologies at Texas Instruments for screening SRAM cells at time zero before they become reliability issues

Scalability of a trench capacitor cell for 64 Mbit DRAM

The authors address cell leakage issues and conclude that a unique field-plate isolated trench capacitor cell structure, already demonstrated at the 16-Mb level with over 1 s of data retention (50% bit fail measured at 90 degrees C), is scalable to 64-Mb DRAM (dynamic RAM). As the trench size is reduced to 0.6 mu m, the trench curvature helps reduce the trench-to-trench punch-through leakage. Substrate concentration of approximately 10/sup 17/ cm/sup -3/ is sufficient to suppress the punch-through current with a 0.5- mu m trench spacing. Diode and gate-induced breakdown voltages remain well above the operating voltage. Trench capacitor dielectric is scalable to less than 5-nm equivalent oxide thickness.<<ETX>>

Design, mask, and manufacturability

The ability to transfer designs with high fidelity onto photomasks and then to silicon is an increasingly complex task for advanced technology nodes. For example, the majority of the critical layers for even the 130nm node are patterned by sub-wavelength photolithography; therefore, the numerical aperture, illumination condition, and the resist process must be optimized to achieve the necessary resolution. The reticle, as a bridge between design and process, has become very complex due to the extensive application of resolution enhancement technologies (RETs). As the complexity of RETs increases, the final mask data can be vastly different from the original design due to a series of data manipulations. Optimizing the reticle layout plays the pivotal role in design-for-manufacturability (DFM) considerations. In this paper, we will discuss how design rules must accommodate the needs of Optical Proximity Correction (OPC) and Phase-shifting Masks (PSM). The final layout on a mask after extensive polygon manipulation must also meet the capability and manufacturability of mask writing, mask inspection, and silicon processing. We will also discuss how the wafer fabs perspective can affect the mask shop. Throughout the discussion, we will demonstrate that the integration at mask level and the collaboration of design, RET, mask shop, and wafer fab are key to DFM success.