Gishi Chung

Scalability of a trench capacitor cell for 64 Mbit DRAM

The authors address cell leakage issues and conclude that a unique field-plate isolated trench capacitor cell structure, already demonstrated at the 16-Mb level with over 1 s of data retention (50% bit fail measured at 90 degrees C), is scalable to 64-Mb DRAM (dynamic RAM). As the trench size is reduced to 0.6 mu m, the trench curvature helps reduce the trench-to-trench punch-through leakage. Substrate concentration of approximately 10/sup 17/ cm/sup -3/ is sufficient to suppress the punch-through current with a 0.5- mu m trench spacing. Diode and gate-induced breakdown voltages remain well above the operating voltage. Trench capacitor dielectric is scalable to less than 5-nm equivalent oxide thickness.<<ETX>>