Donald J. Coleman

Interface trap-enhanced gate-induced leakage current in MOSFET

Interface traps are shown to significantly affect the gate-induced drain-leakage current in a MOSFET or gated diode. The leakage current in a p/sup +/-gated diode can increase by two orders of magnitude when the interface trap density is increased from 10/sup 11/ to 10/sup 12/ cm/sup -2/-eV/sup -1/. The fact that thermal annealing at 300 degrees C can eliminate both the generated interface traps and the excessive leakage current supports the close correlation between the two. The p/sup +/-gated diode is found to be more susceptible to this interface-trap related leakage current than the n/sup +/-device, which can be explained qualitatively by an interface-trap-assisted tunneling model.<<ETX>>

Gate current injection initiated by electron band-to-band tunneling in MOS devices

A substrate hot-electron injection across the gate oxide initiated by electron band-to-band tunneling in p-type silicon is discussed. The injection electrons are generated by the energetic holes which are originally left behind by the band-to-band tunneling electrons. The injection can be easily controlled by an appropriate bias to a nearby n/sup +/ diffusion, and the injection efficiency can be as high as 10/sup -2/. Due to the small oxide field during injection, the electron fluence through the oxide before failure is much higher than under a Fowler-Nordheim tunneling stressing. These advantages make this band-to-band tunneling induced substrate hot-electron injection a possible programming mechanism for nonvolatile memories.<<ETX>>

Scalability of a trench capacitor cell for 64 Mbit DRAM

The authors address cell leakage issues and conclude that a unique field-plate isolated trench capacitor cell structure, already demonstrated at the 16-Mb level with over 1 s of data retention (50% bit fail measured at 90 degrees C), is scalable to 64-Mb DRAM (dynamic RAM). As the trench size is reduced to 0.6 mu m, the trench curvature helps reduce the trench-to-trench punch-through leakage. Substrate concentration of approximately 10/sup 17/ cm/sup -3/ is sufficient to suppress the punch-through current with a 0.5- mu m trench spacing. Diode and gate-induced breakdown voltages remain well above the operating voltage. Trench capacitor dielectric is scalable to less than 5-nm equivalent oxide thickness.<<ETX>>

Extensions of the effective thickness theory of oxide breakdown

The effective thickness concept of oxide breakdown is generalized to a causal time-to-breakdown function, depending only on effective electric field. The function is approximated by a linear and inverse exponential electric-field dependence and applied differentially to data obtained in a pair of step stress tests. The effective thickness distribution is evaluated in both cases and found to be independent of the form chosen. The actual electric-field dependence of the time-to-breakdown function is measured and can be fit with either form over the small range of effective electric fields encountered in the highly accelerated tests. The analysis technique using a pair of tests is presented to illustrate that the effective thickness theory does not require a particular form for the time-to-breakdown function. It demonstrates that the defect density function can be fully obtained at highly accelerated conditions, sampling only a small range of high electric fields. The technique does not of itself allow extrapolation to lower electric fields even though the distribution in effective thickness is known. >