Ranganathan Nagarajan

TSV interposer fabrication for 3D IC packaging

In this paper, Through silicon via (TSV) based interposer fabrication processes for 3D stack packaging has been presented. An interposer test chip of 25 × 25 mm size, has been designed with full array TSVs of 50 um size vias at 300 um pitch. TSVs of aspect ratio 4 are formed on 8 inch wafer using DRIE process and these vias are isolated by thermal oxide, followed by barrier/seed layer of Ti/Cu deposition. TSVs are filled with solid copper (Cu) using optimized pulse reverse damascene electroplating and Cu chemical mechanical polishing (CMP) process also developed to remove the over burden copper with minimum dishing. Multi layer front side metallization process has been demonstrated using electroplated Cu as re-distribution layers (RDL) and spin-on-dielectrics as RDL passivation. Solid Cu filled TSVs are exposed at the backside of the TSVs using backgrinding and Cu CMP. Thin wafer handling process was developed for backside metallization on 200 um thick interposer wafers using support wafer with temporary adhesive bonding. Low temperature dielectric process has been optimized for backside via passivation to isolate the vias from surrounding silicon and backside RDL process as temporary adhesive can not withstand for high temperature processes. The support wafer is de-bonded by sliding at high temperature, followed by cleaning of temporary adhesive material on the front side of interposer wafer using cleaning chemical. TSV interposer of 200um thickness has been fabricated successfully and the vias are in very good connectivity from the top to the bottom. Complete interposer fabrication process issues and solutions have been discussed.

Development of a novel deep silicon tapered via etch process for through-silicon interconnection in 3-D integrated systems

A novel dual etch process technology has been demonstrated which provides an opportunity to precisely and independently control the etch throughput and required via slope that is required to achieve conformal deposition of dielectric, copper diffusion barrier and copper seed metallization. It is further shown how a void-free copper via plating has been achieved for implementation into 3-D integrated systems

Design, process integration and characterization of wafer level vacuum packaging for MEMS resonator

This paper discusses wafer level vacuum sealing technology with evaporated AuSn solder for a microelectromechanical systems (MEMS) resonator without getter material. The MEMS resonator is fabricated and characterized in a vacuum chamber. Relationship between the Q-factor of the MEMS resonator and the vacuum level is established and used as a reference for later vacuum level calibration. Wafer bonding using evaporated AuSn solder is performed in an EVG wafer bonder. With optimized bonding conditions, the achieved shear strength is higher than 59 MPa and uniform cross-section of the bonding ring has been achieved. The calculated He leakage rate is between 10−13 atm cc/s and 10−14 atm cc/s. By comparing the measured Q-factor of packaged resonator with the reference curve, the corresponding vacuum level is 0.2 Torr. Reliability tests results show that shear strength decreases for 7% and still high enough for real application. The vacuum level after reliability tests is comparable to that of long term vacuum level.

Design, fabrication and testing of wafer level vacuum package for MEMS device

A wafer level vacuum package with getters deposited on the cap wafer is developed for an accelerometer device. An accelerometer wafer and cap wafer is bonded together in a vacuum of 1 milli torr and is characterized using a MEMS motion analyzer (MMA). Vacuum inside the package is measured indirectly by measuring the Q factor response of the accelerometer structure inside the package. The obtained results indicated that there is variation from the center to the edge of the wafer. This may be due to difference in the outgassing of the package. Different reliability tests on the wafer level package showed the package is robust to the reliability conditions. A progressive test on Q factor for different cycles of reliability test proven that there is no shift in the measurement value. A 3D wafer level package for accelerometer device is also developed to meet the requirements of vacuum packaging. Hermeticity and CV test showed that no degradation in the device performance when subjected to reliability tests

Development of low temperature PECVD nitride with low stress and low etch rate in BOE solution for MEMS applications

This paper presents the development of a low temperature silicon nitride deposition process using plasma enhanced chemical vapor deposition (PECVD) system. The nitride films showed low stresses ranging from compressive to tensile and very low etch rates in the buffered oxide etch (BOE) solution. These nitride films can be used as MEMS structure materials where suspended structures are involved. In this work, individual process parameters such as SiH4/H2/N2 gas flows, chamber pressures, temperatures and HF powers that related to the nitride film stress and etch rate in BOE solution are also investigated.

Conformal low -temperature dielectric deposition process below 200°C for TSV application

A detailed study to perform low temperature (< 200°C) PECVD TEOS-oxide deposition process with very low mechanical stress and good conformal deposition on high aspect ratio features (10∶1) was done. Individual conditions that affect the oxide stress and deposition rate such as TEOS & O2 flow rate, HF/LF power, pressure and temperature are investigated. The optimal conditions found are used to then deposited into trenches and further fine tuned to give excellent step coverage for high aspect ratio features.

Modification of photoresist profile in lift-off process for MEMS application

A CMOS compatible single resist layer lift-off process for forming patterns on a substrate is described. Unlike in most other methods, an ion bombardment is employed here to harden the top of the resist leaving the sidewall of the resist unaffected. The resist is then treated to a low temperature O2 plasma etching process to achieve a T-shaped undercut profile. This process is found to be simple, repeatable and controllable. Resist profile with adjustable overhang length and the sidewalls of the resist profile with an almost T-shape could be achieved with the help of the process described in the current work. Such increased overhang length prevents metallization of the sidewalls of the resist, and thus facilitates more rapid removal of the resist during lift-off. The process starts from a patterned resist layer having vertical resist profile. It is then subjected to Ion bombardment to harden the top surface of the resist leaving the sidewalls unaffected. The ions are directed at sufficient dose and energy to cause the top of the resist mask to get hardened. Subsequently, the resist patterns are subjected to a low temperature isotropic plasma etching process resulting in an under-cut T-shaped resist profile. This process is highly suitable for MEMS application where metals like Cr, Au, Cu etc are frequently used but are difficult to dry etch.

Development of Multiple-Step SOI DRIE Process for Superior Notch Reduction at Buried Oxide

A novel two step etch process using the Bosch-etch mechanism to prevent notching on an SOI wafer is presented. The first etch step is used to attain the maximum etch depth with high etch rate and stop before the buried oxide (BOX). Followed by the second etch step with lower etch rate and tuned to soft land on the BOX to etch the remaining depth. In addition to that it is tailored to also provide a tapered etch profile which is beneficial in reducing the notch if over etching occurs.

Development of high aspect ratio via filling process for 3D packaging application

This paper presents our development work to achieve high aspect ratio void-free polymer via filling with various types of organic materials for potential application in 3D wafer level packaging. This study focuses on the development of via filling process using the conventional spin-coating and curing process. Thermoplastic polymers have been selected for this evaluation due to its ability to reflow and fill gaps easily. Test wafers with circular via patterns with diameters from 1–70 µm with aspect ratios from 1–10 have been evaluated. The various challenges to achieving void-free via filling have been presented and it has been demonstrated that a void-free filling is feasible for vias with aspect ratio of 1–8.

Development of radio-opaque silicon micro needles for medical diagnostics

In this paper, a method of fabricating radio opaque silicon micro needles for tissue labeling applications is reported. Cylindrical shaped micro needles ranging from 7 × 7 to 11 × 11 arrays with a pitch varying from 60 µm to 100µm are fabricated in silicon using a three step mask process. A backside cavity is generated under DRIE for filling the radiopaque material. Barium sulphate is filled in and a biocompatible sealing is provided to hold the radiopaque material inside. The fabricated needles provide a better contrast enhancement under x-ray imaging.