Pinjala Damaruganath

TSV interposer fabrication for 3D IC packaging

In this paper, Through silicon via (TSV) based interposer fabrication processes for 3D stack packaging has been presented. An interposer test chip of 25 × 25 mm size, has been designed with full array TSVs of 50 um size vias at 300 um pitch. TSVs of aspect ratio 4 are formed on 8 inch wafer using DRIE process and these vias are isolated by thermal oxide, followed by barrier/seed layer of Ti/Cu deposition. TSVs are filled with solid copper (Cu) using optimized pulse reverse damascene electroplating and Cu chemical mechanical polishing (CMP) process also developed to remove the over burden copper with minimum dishing. Multi layer front side metallization process has been demonstrated using electroplated Cu as re-distribution layers (RDL) and spin-on-dielectrics as RDL passivation. Solid Cu filled TSVs are exposed at the backside of the TSVs using backgrinding and Cu CMP. Thin wafer handling process was developed for backside metallization on 200 um thick interposer wafers using support wafer with temporary adhesive bonding. Low temperature dielectric process has been optimized for backside via passivation to isolate the vias from surrounding silicon and backside RDL process as temporary adhesive can not withstand for high temperature processes. The support wafer is de-bonded by sliding at high temperature, followed by cleaning of temporary adhesive material on the front side of interposer wafer using cleaning chemical. TSV interposer of 200um thickness has been fabricated successfully and the vias are in very good connectivity from the top to the bottom. Complete interposer fabrication process issues and solutions have been discussed.

Effect of TSV interposer on the thermal performance of FCBGA package

In this paper, the effect of TSV (Through Silicon Via) parameters on the equivalent thermal conductivity of TSV interposer and the effect of the TSV interposer on the thermal performance of the package have been elaborated. The modeling approach using in this paper includes compact modeling for the package and detailed modeling for the TSV interposer. The objective of compact modeling is to study the effect of TSV interposer on thermal performance of the package, while the objective of detailed modeling is to extract the equivalent thermal conductivity of TSV interposer which is used for compact modeling. The proposed package in this study includes a large die with fine pitch, a silicon interposer with TSV, a 1-2-1 buildup substrate and a PCB board. In addition, to evaluate the thermal performance of the proposed package, a similar package without the TSV interposer is also modeled in this study for comparison. The results of detailed modeling show that the equivalent thermal conductivity of TSV interposer can be increased by reducing the pitch and via ratio of TSV, as well as increasing the plating thickness of partial filled TSV and using highly conductive filler material. Furthermore, the results of compact modeling reveal that the proposed TSV interposer improves the thermal performance of the package. The thermal resistance of the package decreases when the interposer size and thickness increase, and the equivalent thermal conductivity of TSV interposer has negligible effect on thermal performance of the package.

Development of Large Die Fine-Pitch Cu/Low-

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-μm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.

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This paper presents the assembly optimization and charcterierization of Through-Silicon Vias (TSV) interposer technology for two 8 × 10mm2 micro-bumped chips. The two micro-bumped chips represent different functional dies in a System-in-package (SiP). In the final test vehicle, one of the micro-bumped chips had 100μm bump pitch and 1,124 I/O; the other micro-bumped chip had 50μm bump pitch and 13,413 I/O. The TSV interposer size is 25 × 25 × 0.3mm3 with CuNiAu as UBM on the top side and SnAgCu bumps on the underside. The conventional substrate size is 45 × 45mm2 with 1-2-1 layer configuration, a ball-grid array (BGA) of 1mm pitch and a core thickness of 0.8mm. The final test vehicle was subjected to MSL3 and TC reliability assessment. The objective of this paper was to incorporate two 8 × 10mm2 micro-bumped chips into TSV interposer. The micro-bumped chips should have no underfill voiding issue and the whole package should be able to pass Moisture Sensitivity Level 3 (MSL3) and Thermal Cycling (TC) reliability assessment. To achieve this objective of incorporating micro-bumped chips into the TSV interposer, the challenges were small standoff height/ low bump pitch of the micro-bumped chip, underfill flowability and its reliability performance. To overcome these challenges, different types of capillary flow underfill, bump layout designs and bump types were evaluated and a quick reliability assessment was used to select the materials and test vehicle parameters for final assembly and reliability assessment.

FCBGA Package With Through Silicon via (TSV) Interposer

This paper discusses wafer level vacuum sealing technology with evaporated AuSn solder for a microelectromechanical systems (MEMS) resonator without getter material. The MEMS resonator is fabricated and characterized in a vacuum chamber. Relationship between the Q-factor of the MEMS resonator and the vacuum level is established and used as a reference for later vacuum level calibration. Wafer bonding using evaporated AuSn solder is performed in an EVG wafer bonder. With optimized bonding conditions, the achieved shear strength is higher than 59 MPa and uniform cross-section of the bonding ring has been achieved. The calculated He leakage rate is between 10−13 atm cc/s and 10−14 atm cc/s. By comparing the measured Q-factor of packaged resonator with the reference curve, the corresponding vacuum level is 0.2 Torr. Reliability tests results show that shear strength decreases for 7% and still high enough for real application. The vacuum level after reliability tests is comparable to that of long term vacuum level.

Assembly and reliability of micro-bumped chips with Through-silicon Vias (TSV) interposer

Thermal management in 3D packaging is a critical factor to be considered in enabling this technology to be exploited further. Heat density in excess of 100 W/cm2 can be achieved due to the smaller footprint of such packages. Liquid cooling through microchannels embedded within the package had been shown to improve the thermal characteristics of packages. In this work, a liquid cooling solution is designed with emphasis on the flow distribution through the microchannels. The use of a reducing plenum design had been shown to lower the pressure drop requirement while improving the thermal characteristics. The thermal implication with achieving deep channels through the DRIE process is an introduction of a significant thermal resistance to the overall thermal network. Numerical modeling of the actual physical components in the cooling module had also being done to evaluate the system operating points and hence sizing the pump. The approach taken in this work identified the issues faced when embedding heat transfer features within the package and in a cooling solution. The system modeling had also been shown to provide a good estimate of the operating conditions within the physical module.

Design, process integration and characterization of wafer level vacuum packaging for MEMS resonator

In this paper, a Via in Mold (ViM) interconnects were developed for embedded wafer level package (EMWLP) to enable 3D application. ViM interconnects are essentially plated blind vias drilled into the mold compound substrate. The two key processes required for ViM development are laser drilling of blind vias and Cu seed layer deposition. Mold compound is a composite material made up of epoxy resin and filler particles. The non-uniform distribution of filler particles in the matrix will make consistent laser drilling results difficult to achieve. Laser drilling process parameters were optimized such that the drilling depth is stopped at the Cu metallization pads without damaging the metallization. The sidewall roughness of laser drilled vias makes it difficult for physical vapor deposition process to achieve a conformal seed layer. In order to overcome issues with rough vias sidewall, an electroless Cu plating process was adopted. Electroless Cu plating process was optimized to deposit a conformal Cu seed layer along the sidewall. Electrolytic Cu plating was used to build up the electroless Cu seed layer to the desired thickness for electrical connection. A test vehicle which consists of 50 via-chains was fabricated using the optimized process parameters. The via-chains electrical resistance was measured to extract the resistance of a single ViM. From the electrical resistance measurement, the resistance for a single ViM is ∼0.02 Ω.

Thermal and Hydraulic Design and Characterization of a Liquid-Cooled 3D Silicon Module

A disposable polydimethylsioxane package is developed for ‘Bio-Microfluidic System’. Disposable Bio-Microfluidic system avoids the contamination of the system after each use and this requires the use of low cost materials. Polydimethylsioxane (PDMS) is an attractive low cost material for making substrates of the micro-fluidic package. The disposable PDMS Package consists of PDMS substrates, which are fabricated by soft-lithography. The PDMS substrates are bonded together to form the disposable package with the use of a thin-film, coated both side with adhesive material. The adhesive material is selected by chemical soaking test, peel test and bio-analysis. The tests reveal that the adhesive material can handle all chemical reagents without causing blockage or discoloration to the package. The disposable PDMS package uses a plug-in concept as the macro-micro fluidic interconnects that allows easy detachment of package from the external fluidic system. The developed disposable PDMS package has demonstrated a fluidic leak-proof package that handles up to 100kPa pressure with flow-rate of 200µl/min. The package has also demonstrated that it can filter out Viral Ribonucleic Acids (RNA) from spiked blood sample. This micro fluidic package forms an integral part of the bio micro fluidic system.

Development of Via in Mold (ViM) for embedded wafer level package (EWMLP)

A dry film photoresist was selected as the sacrificial material for a metal lift off process. However, a weak and inconsistent adhesion of the evaporated under bump metallurgy (UBM) and solder on the passivation surface was observed during the dry film stripping process. This problem may be due to the poor negative profile (88 to 89 degrees) of the patterned dry film side wall after dry film developing, resulting to inconsistent metal lift off. A few dry film predevelopment and post development parameters are identified and tested from the standard dry film development process, to obtain a negative profile of the dry film to be less than 84 degrees. After each test, cross section of the patterned dry film side wall is observed under a microscope to check if a negative profile is obtained. The 50μm thick dry film at 35mJ/cm2 with other modifications of the process gives the best results

Disposable Polydimethylsioxane Package for 'Bio~Microfluidic System'

Large core step-index plastic optical fibers (SI-POF) are bandwidth limited due to their high modal dispersion and coupling loss at the receiver. To date, the large core SI-POF are typically deployed up to 150 Mb/s applications. This paper reports the transmission of 2.5 Gb/s on 980 μm core step-index plastic optical fiber with fiber-based mode conditioning elements that are part of the connector assembly. The built-in mode conditioners are tapered fiber tips that provide restricted mode launching at transmitter and mode filtering at the receiver side. The structures, at the tip of POF, are optimized by optical simulations and fabricated using laser fusion process. The connector assembly is realized by precisely encapsulating the mode conditioners with a metallic ferrule and positioned using optical grade epoxies. These plug-in modules are inserted to a typical SFP transceiver LC connector receptacle and characterized for gigabit rates.