Raul A. Perez

A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation

This paper presents a low-dropout regulator (LDO) for portable applications with an impedance-attenuated buffer for driving the pass device. Dynamically-biased shunt feedback is proposed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed to high frequencies without dissipating large quiescent current. By employing the current-buffer compensation, only a single pole is realized within the regulation loop unity-gain bandwidth and over 65deg phase margin is achieved under the full range of the load current in the LDO. The LDO thus achieves stability without using any low-frequency zero. The maximum output-voltage variation can be minimized during load transients even if a small output capacitor is used. The LDO with the proposed impedance-attenuated buffer has been implemented in a 0.35-mum twin-well CMOS process. The proposed LDO dissipates 20-muA quiescent current at no-load condition and is able to deliver up to 200-mA load current. With a 1-muF output capacitor, the maximum transient output-voltage variation is within 3% of the output voltage with load step changes of 200 mA/100 ns.

A Transient-Enhanced 20μA-Quiescent 200mA-Load Low-Dropout Regulator With Buffer Impedance Attenuation

This paper demonstrates a 200mA low-dropout regulator (LDO) for portable applications. Buffer impedance attenuation is developed to realize a single-pole loop response through shunt feedback. The LDO is thus unconditionally stable without using an ESR zero and output undershoots and overshoots are minimized during load transients. Implemented in 0.35μm twin-well CMOS, the LDO only dissipates 20μA quiescent current. With a 1μF output capacitor, the maximum transient-output variation is 54mV with full-load step change of 200mA.

Design of an adjustable, low voltage, low dropout regulator

This paper presents the design of a low voltage, low dropout (LDO) regulator with two different output voltages (1V or 1.8V). The basic function of an LDO is to optimize the battery life of portable devices and to provide a constant output voltage to drive small sub-circuits. The proposed LDO was designed using 0.35/spl mu/m CMOS technology. The design is able to drive a load of up to 50mA with a maximum dropout voltage of only 200mV. A low quiescent current (at no load) of approximately 23/spl mu/A, makes this a low power design.