Feng Zhu

Metal gate-HfO/sub 2/ MOS structures on GaAs substrate with and without Si interlayer

In this letter, we studied the effects of post-deposition anneal (PDA) time and Si interface control layer (ICL) on the electrical characteristics of the MOS capacitor with high-/spl kappa/ (HfO/sub 2/) material on GaAs. Thin equivalent oxide thickness (EOT<3 nm) with excellent capacitance-voltage (C-V) characteristics has been obtained. The thickness of the Si ICL and PDA time were correlated with C-V characteristics. It was found that high temperature Si ICL deposition and longer PDA time at 600/spl deg/C improved the C-V shape, leakage current, and especially frequency dispersion (<5%).

Ultrathin HfO2 (equivalent oxide thickness=1.1nm) metal-oxide-semiconductor capacitors on n-GaAs substrate with germanium passivation

We present the capacitance-voltage characteristics of TaN∕HfO2∕n-GaAs metaloxide-semiconductor capacitors, with an equivalent oxide thickness (EOT) of 10.9A, low frequency dispersion, and a low leakage current density (Jg) of ∼10−6A∕cm2 at ∣VG−VFB∣=1V. Physical vapor deposited high-k dielectric film (HfO2) and a thin germanium (Ge) interfacial control layer (ICL) were used to achieve the low EOTs. As postdeposition annealing (PDA) time increases beyond a critical point, EOT and Jg also abnormally increase due to the degradation of the interface between Ge and GaAs surface, which was well indicated in electron energy loss spectroscopy, energy dispersive x-ray spectroscopy, and transmission electron microscopy analyses. Results indicate that a thin Ge ICL, optimized conditions for PDA, as well as high-k material (HfO2) play important roles in allowing further EOT scale down and in providing a high-quality interface.

A simple approach to fabrication of high-quality HfSiON gate dielectrics with improved nMOSFET performances

A simple technique to form high-quality hafnium silicon oxynitride (HfSiON) by rapid thermal processing oxidation of physical vapor deposition hafnium nitride (HfN) thin films on ultrathin silicon oxide (SiO/sub 2/) or silicon oxynitride (SiON) layer is presented. Metal TaN gate electrode is also introduced into such HfSiON stacks. Excellent performances including large electron mobility (85%SiO/sub 2/at0.2 MV/cm), low leakage current (10/sup -4/ of SiO/sub 2/), and superior time-dependant dielectric breakdown reliability are achieved in HfSiON/SiO/sub 2/ stacks, and these results suggest such stacks are very promising for the low-power SOC applications in the near future. In addition, the improvement of the electron mobility in this HfSiON/SiO/sub 2/ stack by a reduction of the border traps in the HfSiON dielectric is demonstrated.

Structural advantage for the EOT scaling and improved electron channel mobility by incorporating dysprosium oxide (Dy/sub 2/O/sub 3/) into HfO/sub 2/ n-MOSFETs

A structural approach of fabricating laminated Dy₂O₃-incorporated HfO₂ multimetal oxide dielectric has been developed for high-performance CMOS applications. Top Dy₂O₃ laminated HfO₂ bilayer structure shows the thinnest equivalent oxide thickness (EOT) with a reduced leakage current compared to HfO₂. This structure shows a great advantage for the EOT scaling CMOS technology. Excellent electrical performances of the Dy₂O₃/HfO ₂ multimetal stack oxide n-MOSFET such as lower V_T, higher drive current, and an improved channel electron mobility are reported. Dy₂O₃/HfO₂ sample also shows a better immunity for V_t instability and less severe charge trapping characteristics. Two different rationed Dy ₂O₃/HfO₂ and HfO₂ n-MOSFET were measured by charge-pumping technique to obtain the interface state density (D_it), which indicates a reasonable and similar interface quality. Electron channel mobility is analyzed by decomposing into three regimes according to the effective field. Reduced phonon scattering is found to be the plausible mechanism for higher channel mobility

Inversion-Type InP MOSFETs with EOT of 21 Å Using Atomic Layer Deposited Al2O3 Gate Dielectric

We present results on n-channel inversion-type InP metal-oxide-semiconductor field-effect transistors (MOSFETs) with atomic-layer-deposited Al 2 O 3 gate dielectric using the gate-last process. InP MOSFETs with an equivalent oxide thickness (EOT) of 21 A were realized with high performance including a drive current of 50 mA/mm, an extrinsic transconductance of 44.2 mS/mm, a subthreshold swing of 90 mV/dec, and a peak effective electron mobility of 745 cm 2 /Vs for a 50 μm gate length. The transmission electron microscopy and X-ray photoemission spectroscopy measurements demonstrate an interface between Al 2 O 3 and InP substrates with high quality and good thermal stability. The effects of fast and slow traps on the transistor performance have also been investigated using constant electrical stress measurements and pulse measurements.

A high performance In0.53Ga0.47As metal-oxide-semiconductor field effect transistor with silicon interface passivation layer

In this letter, we demonstrate a high performance In0.53Ga0.47As channel n-type metal-oxide-semiconductor field effect transistor with silicon interface passivation layer (IPL) and HfO2 gate oxide. Owing to the effectiveness of Si IPL on improving the interface quality, good device characteristics have been obtained, including the peak transconductance of 7.7 mS/mm (Lg=5u2002μm and Vd=50u2002mV), drive current of 158 mA/mm (Lg=5u2002μm, Vgs=Vth+2u2002V, and Vd=2.5u2002V), and the peak effective channel mobility of 1034u2002cm2/Vu2009s. As an important factor on device design, the impact of silicon IPL thickness on the transistor characteristics has been investigated.

Fabrication of TaN-gated ultra-thin MOSFETs (EOT <1.0 nm) with HfO/sub 2/ using a novel oxygen scavenging process for sub 65 nm application

We developed a novel process to achieve ultra-thin gate dielectrics (EOT <0.7 nm) without involving nitrogen incorporation by engineering interface oxide thickness for sub 65nm high-performance logic technology node. Interfacial oxide formation was suppressed by the oxygen-scavenging effect using Hf metal on underlying HfO/sub 2/ device structure with appropriate annealing. The scavenging Hf metal layer consumes oxygen sources leading to further scaling still using undoped HfO/sub 2/. Using this fabrication approach, EOT of /spl sim/0.9 nm after conventional self-aligned MOSFET process was successfully obtained. In addition, further EOT improvement (EOT: 0.55-0.60nm) was realized in conjunction with nitrogen incorporation using scavenging effect.

High mobility HfO2-based In0.53Ga0.47As n-channel metal-oxide-semiconductor field effect transistors using a germanium interfacial passivation layer

The electrical characteristics of HfO2-based n-channel metal-oxide-semiconductor field effect transistors (MOSFETs) and metal-oxide-semiconductor capacitors (MOSCAPs) on high indium content In0.53Ga0.47As channel layers are presented. N-channel MOSFETs with a germanium (Ge) interfacial passivation layer (IPL) show maximum mobility 3186u2002cm2/Vu2009s from split capacitance-voltage (C-V) method and the normalized drain current (to the channel length of 1u2002μm) of 753 mA/mm at Vg=Vth+2u2002V and Vd=2u2002V. On the contrary, MOSFETs without a Ge IPL or with high temperature post-metal annealing (PMA) exhibit inferior characteristics. MOSCAPs on n-type In0.53Ga0.47As layers demonstrate excellent C-V characteristics including low C-V frequency dispersion and low dielectric leakage current.

Importance of controlling oxygen incorporation into HfO2∕Si∕n-GaAs gate stacks

The interfacial change of HfO2∕Si∕n-GaAs gate stacks after high temperature annealing has been characterized using x-ray photoelectron spectroscopy (XPS), photoluminescence (PL), and capacitance-voltage measurement. The properties of the interface are sensitive to the amount of incorporated oxygen. XPS measurement shows the formation of gallium and arsenic oxides with increasing annealing temperature. A PL emission from the Si interfacial passivation layer was observed after 900°C annealing. With more oxygen incorporation, this PL emission was quenched. The measurement of the interface state density proved the generation of deep traps with too much oxygen incorporation. Depletion-mode metal-oxide-semiconductor field effect transistors using postdeposition annealing at 600°C with and without post-metal-annealing at 900°C have also been fabricated and characterized. Too much oxygen incorporation resulted into the degradation of mobility, subthreshold swing, and transconductance. The interfacial gallium and ...

Effect of channel doping concentration and thickness on device performance for In0.53Ga0.47As metal-oxide-semiconductor transistors with atomic-layer-deposited Al2O3 dielectrics

We have investigated the channel doping concentration and channel thickness dependence of device performance for In0.53Ga0.47As metal-oxide-semiconductor transistors with atomic layer deposited Al2O3 dielectrics. We found that undoped channel provides the highest drive current of 125 mA/mm for 5u2002μm gate length. With proper substrate doping concentration (5×1016/cm3), reasonable subthreshold swing (104 mV/decade) can be achieved for 4.7 nm equivalent oxide thickness. Thinner InGaAs channel exhibits lowest off-current density of 4.0×10−6u2002mA/mm.