Charles H. Stapper

Integrated circuit yield statistics

The random failure statistics for the yield of mass-produced semiconductor integrated circuits are derived by considering defect and fault formation during the manufacturing process. This approach allows the development of a yield theory that includes many models that have been used previously and also results in a practical control model for integrated circuit manufacturing. Some simpler formulations of yield theory that have been described in the literature are compared to the model. Application of the model to yield management are discussed and examples given.

Modeling of defects in integrated circuit photolithographic patterns

In a previous paper by the same author the foundation was laid for the theory of photolithographic defects in integrated circuits. This paper expands on the earlier one and shows how to calculate the critical areas and probability of failure for dense arrays of wiring. The results are used to determine the nature of the defect size distribution with electronic defect monitors. Several statistical techniques for doing this are described and examples are given.

Modeling of integrated circuit defect sensitivities

Until now only cursory descriptions of mathematical models for defect sensitivities of integrated circuit chips have been given in the yield literature. This paper treats the fundamentals of the defect models that have been used successfully at IBM for a period of more than fifteen years. The effects of very small defects are discussed first. The case of photolithographic defects, which are of the same dimensions as the integrated circuit device and interconnection patterns, is dealt with in the remainder of the paper. The relationships between these models and test sites are described. Data from measurements of defect sizes are discussed.

Defect density distribution for LSI yield calculations

The experimental determination of defect density distributions is described. These distributions are needed for calculating LSI yields. The defect densities appear to be distributed according to gamma distributions. An expression for the average yield for a semiconductor process is derived based on the results.

A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC

A high-speed 16-Mb DRAM chip with on-chip error-correcting code (ECC), which supports either 11/11 or 12/0 RAS/CAS addressing and operates on a 3.3- or 5-V power supply, is described. It can be packaged as a 2-Mb*8, 4-Mb*4, 8-Mb*2, or 16-Mb*1 DRAM, And is capable of operating in fast page mode, static column mode, or toggle mode. Speed and flexibility are achieved by a pipeline layout and on-chip SRAMs that buffer entire ECC words. The use of redundant word and bit lines in conjunction with the ECC produces a synergistic fault-tolerance effect. >

Integrated circuit yield management and yield analysis: development and implementation

Integrated circuit manufacturing yields are not necessarily a function of chip area. Accurate yield analysis shows how the yield depends on circuit design and layout. By determining the probabilities of failure and critical areas for different defect types, it is possible to control and manage the yield of integrated circuits. This includes the manufacture of DRAMs, SRAMs, CMOS logic, ASICs, and CMOS and biCMOS microprocessors. Examples explain the method of meeting yield objectives by setting targets for yield components. In addition, the yield management approach allows for a systematic allocation of resources. Required defect-density learning determines the contamination levels for clean rooms and process equipment. >

LSI yield modeling and process monitoring

This paper describes an analytical technique for quantifying and modeling the frequency of occurrence of integrated circuit failures. The method is based on the analysis of random and clustered defects on wafers with defect monitors. Results from pilot line data of photolithographic defects, insulator short circuits, and leaky pn junctions are presented to support the practicality of the approach. It is shown that, although part of the yield losses are due to the clustering of defects, most product loss is from random failures. The yield model shows good agreement with actual product yields. Introduction Relatively little has been published about he actual causes of yield losses in large scale integrated circuits. Yet he successful production of LSI semiconductor products depends on the elimination of failures caused by simple open circuits in conductors, short circuits between conductors, and missing or misaligned contact holes in integrated circuits. This paper describes a statistical method for quantifying the components of the product yield in a semiconductor process. Estimates are made for the yields associated with open and short circuits in various conductive layers, short circuits in insulator layers, and the breakdown of junctions. The estimates result from statistical manipulation of data obtained using defect monitors that are sensitive only to a particular type of defect. Therefore, the data can be used to estimate the defect densities causing the various types of open and short circuits. The defect densities, in turn, can then be used to calculate the corresponding product yields. The yield for each yield detractor was calculated using known techniques [ 1 81. In most of these cases, however, the yield models were applied to some total defect density, which tended to mask the major yield detractors and obscure the sources of yield losses. Measuring and modeling each type of defect individually, as described in this paper, allows the evaluation of all yield detractors. Major yield problem areas are thus exposed, and solutions to these problem areas can be sought. To study the statistics of failure mechanisms, the special defect monitors were used to detect short circuits and open circuits in conductors and pinholes in the dielectrics between the conductive layers. This detection was done by measuring the conductivity of the monitors with an automatic tester. Back-biased diffusions were used to study the pn junction leakage in diffused conductors. Alignment detectors, such as those described by Thomas and Presson [9], were also used to study losses due to misalignment. But because these losses were negligible in the study presented here, they are not addressed further. In this paper we first examine the theoretical basis for the analysis. Next we consider the critical areas in which a defect must be centered in order to cause a failure. The experimental procedure is then described, followed by a discussion of results. Finally, a less tedious method is described for obtaining quick estimates of yield. Theoretical basis It was recognized in 1964 by Murphy [ 13 that integrated circuit yields did not follow simple Poisson statistics. His approach using mixed Poisson statistics has been extended by Seeds [2], Ansley [3] , Moore [4] , Warner [ 51, and Stapper [ 61. Yanagawa [ 71 and Gupta, et al. [8] believed that the non-Poisson behavior of LSI failures was due to a radial variation of defect densities, with the higher defect densities causing more failures toward the outer area of the wafers. The Poisson statistics were assumed valid only for local regions on the wafer. It is shown here that there is merit in both methods of yield modeling but that the actual conditions appear to be far more complex in practice than anticipated in any of the theories. However, the data can be handled with a simple extension to existing theory. In a previous study [ 61 it was shown that the number of failing monitors x per wafer could be modeled by the mixed or compound Poisson distribution Prob(X = x ) =lorn q f ( A ) d A . ( 1 ) In that study Eq. ( 1 ) was used for the entire wafer. In our analysis, ( 1 ) is used independently for the inner and ;TAPPER I B M J. RES. DEVELOP. outer zones of the wafer. Therefore, the distribution of A represents a variation in the expected number of failures per zone, rather than in the expected number of failures per wafer, as in [ 61. Distribution ( 1 ) has the useful property that

On a composite model to the IC yield problem

In a recent paper, see ibid., vol. Sc-9, no.3, p.86-95 (1974), Warner proposed a composite model to the monolithic IC yield problem. This composite model is a multiparameter fit to a set of data originally described by Moore (1970). It is shown that these same data can be modeled equally well with negative binomial statistics with two parameters.

Yield Models for Defect-Tolerant VLSI Circuits: A Review

The statistical models for estimating and predicting the manufacturing yields of VLSI circuits are reviewed. It is shown how defect clustering is taken into account, and how yield formulae for defect and fault tolerant VLSI circuits are developed. Different types of formulae for the yield of defect tolerant VLSI circuits have appeared in the literature. It is proven here for the first time that most of these approaches are equivalent.

Large-area fault clusters and fault tolerance in VLSI circuits

Fault-tolerance techniques and redundant circuits have been used extensively to increase the manufacturing yield and productivity of integrated-circuit chips. Presented here is a review of relevant statistical models which have been used to account for the effects on manufacturing yield of the large-area defect and fault clusters commonly encountered during chip fabrication. A statistical criterion is described for determining whether such large-area clusters are present.