Razaidi Hussin

Modelling RTN and BTI in nanoscale MOSFETs from device to circuit: A review

In this paper we summarize the impact of Statistical Variability (SV) on device performances and study the impact of oxide trapped charges in combination with SV. Traps time constants are described and analysed in combination with SV and time dependent simulations are performed including SV, random traps and charge injection stochasticity. Finally we demonstrate the necessity of statistical simulations in extracting compact models of aged devices and we address the problem of aged SRAM cell reliability.

Accurate Simulation of Transistor-Level Variability for the Purposes of TCAD-Based Device-Technology Cooptimization

In this paper we illustrate how the predictive Technology Computer Aided Design (TCAD) process device simulation can be used to evaluate process, statistical, and time-dependent variability at the early stage of the development of new technology. This is critically important for the delivery of accurate early Process Design Kits, including process variability, statistical variability, time-dependent variability (degradation) and their interactions and correlations. This is also critical to the TCAD-based Design-Technology Co-Optimisation (DTCO). To accomplish this task, the fast, large area Coventor virtual fabrication platform SEMulator3D was integrated in the GoldStandradSimulations TCAD-based DTCO tool chain. Published data for Intel 22-nm FinFET technology are used to illustrate and validate the results of the TCAD process and device simulation, the compact model extraction, and the statistical circuit simulation.

Interplay Between Statistical Variability and Reliability in Contemporary pMOSFETs: Measurements Versus Simulations

This paper presents an extensive study of the interplay between as-fabricated (time-zero) variability and gate oxide reliability (time-dependent variability) in contemporary pMOSFETs. We compare physical simulation results using the atomistic simulator GARAND with experimental measurements. The TCAD simulations are accurately calibrated to reproduce the average transistor behavior. When random discrete dopants, line edge roughness, and gate polysilicon granularity are considered, the simulations accurately reproduce time-zero (as-fabricated) statistical variability, as well as time-dependent variability data, represented by threshold voltage shift distributions. The calibrated simulations are then used to predict the reliability behavior at different bias conditions and for different device dimensions.

Reliability aware simulation flow: From TCAD calibration to circuit level analysis

In this paper, we present a simulation flow based on TCAD model calibration against experimental transistor measurement and doping profile reverse engineering. Further the physical astatistical variability simulations at TCAD level are also adjusted to match the statistical measurement. This is folloed up by oxide wear out reliability characterization and modelling. Finally statistical compact model libraries for fresh and aged devices are extracted from large samples of TCAD simulation results allowing the performance analysis of a 6T SRAM cell. The calibration procedure has been performed on P and NMOS transistors fabricated and characterized by IMEC, while Glasgow University performed the TCAD reverse engineering and calibration, and the statistical simulations using dedicated Gold Standard Simulations tools.

Modeling Carrier Mobility in Nano-MOSFETs in the Presence of Discrete Trapped Charges: Accuracy and Issues

This paper investigates the accuracy and issues of modeling carrier mobility in the channel of a nanoscaled MOSFET in the presence of discrete charges trapped at the channel/oxide interface. By comparing drift-diffusion (DD) and Monte Carlo (MC) simulation results, a quasi-local mobility model accounting for the complex scattering profile associated with a trapped carrier at the center of the channel is firstly derived. The accuracy of this model is evaluated on a test-bed 25-nm MOS transistor at low drain bias condition and for several applied gate biases. The issues in extending this mobility model to high drain biases regime and to the case of randomly positioned trapped charges are then discussed in the second part of this paper. Our findings show that DD simulations can maintain computational efficiency and accuracy at low drain biases, when a proper mobility model is used to describe the impact of discrete trapped charges. On the other hand, more complex corrections, that go beyond the simple mobility modification, are necessary to compensate the different carrier concentrations between DD and MC approaches at high drain biases.

Experimental evidences and simulations of trap generation along a percolation path

In this paper we present experimental results of single trap impact on bulk MOSFETs, shedding light on counter intuitive behavior when increasing the gate bias. Using a well calibrated 3D TCAD model, statistical simulations at atomistic level are performed, demonstrating that the interactions between the traps and the percolation path are responsible for the unexpected bias dependences of the trap impact and therefore that a trap generation enhanced by higher current densities along this path can explain measured data.

Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow

This work present the last development of a statistical reliability aware simulation flow from transistors to circuits. A TCAD calibration methodology based on statistical measurement of a 60nm bulk MOSFET is presented. Statistical compact models of fresh and aged transistors are extracted form large ensembles of TCAD simulations results. Compact models representing intermediate stages of degradation, not captured in the TCAD simulations, are interpolated using a proprietary compact model generator. Statistical simulations results for a 6T-SRAM cell aging are presented following various aging scenario for both static noise margin and intrinsic write time.

3D atomistic simulations of bulk, FDSOI and Fin FETs sensitivity to oxide reliability

New architectures introduction succeeded in reducing the device performances dispersion in scaled transistors, but as a consequence the relative importance of oxide reliability increased. In this work we present original results of charged interface traps impact on bulk, FDSOI and Fin FETs performances. Traps time constants are analyzed and recoverable and permanent degradation proportions are derived. Finally transistors parameters dispersion increase with time are simulated demonstrating our simulator ability to provide accurate reliability predictions for these three architectures.

RTN distribution comparison for bulk, FDSOI and FinFETs devices

In this paper we investigate the sensitivity of RTN noise spectra to statistical variability alone and in combination with variability in the traps properties, such as trap level and trap activation energy. By means of 3D statistical simulation, we demonstrate the latter to be mostly responsible for noise density spectra dispersion, due to its large impact on the RTN characteristic time. As a result FinFETs devices are shown to be slightly more sensitive to RTN than FDSOI devices. In comparison bulk MOSFETs are strongly disadvantaged by the statistical variability associated with high channel doping.

TCAD-based methodology for reliability assessment of nanoscaled MOSFETs

The microelectronics industry faces important challenges in reducing technology development and circuit design times. This advocates the use of TCAD approaches to co-optimize circuits and device development. This paper presents the process of calibrating pMOSFET TCAD simulations against measured devices starting with the physical structure, and the doping distribution and achieving good matching of the statistical variability and Random Telegraph Noise (RTN) measurements. The investigated device has been fabricated and characterized by IMEC, while Gold Standard Simulations (GSS) TCAD tools are used to accomplish this task. The calibration includes different channel lengths and widths to capture properly the scaling trends and to match the measured variability and reliability behaviour.