Salvatore Maria Amoroso

Comprehensive Investigation of Statistical Effects in Nitride Memories—Part I: Physics-Based Modeling

This paper presents a comprehensive investigation of statistical effects in deeply scaled nitride memory cells, considering both atomistic substrate doping and the discrete and localized nature of stored charge in the nitride layer. By means of 3-D TCAD simulations, the statistical dispersion of the threshold voltage shift induced by a single localized electron in the nitride is evaluated in presence of non-uniform substrate conduction. The role of 3-D electrostatics and atomistic doping on the results is highlighted, showing the latter as the major spread source. The threshold voltage shift induced by more than one electron in the nitride is then analyzed, showing that for increasing numbers of stored electrons a correlation among single-electron shifts clearly appears. The scaling trend and the practical impact of these statistical effects on cell operation are discussed in Part II of this paper.

Variability Aware Simulation Based Design- Technology Cooptimization (DTCO) Flow in 14 nm FinFET/SRAM Cooptimization

In this paper, we use an automated tool flow in a 14 nm CMOS fin-shaped field-effect transistor (FinFET)/ static random access memory (SRAM) simulation-based design-technology cooptimization (DTCO) including both process-induced and intrinsic statistical variabilities. A 22 nm FinFET CMOS technology is used to illustrate the sensitivity to process-induced fin shape variation and to motivate this paper. Predictive Technology Computer Aided Design (TCAD) simulations have been carried out to evaluate the transistor performance ahead of silicon. Draft-diffusion simulations calibrated to the ensemble Monte Carlo simulation results are used to explore the process and the statistical variability space. This has been enabled by the automation of the tool flow and the dataset handling. The interplay between the process and the statistical variability has been examined in details. A two-stage compact model strategy is used to capture the interplay between process and statistical variability. To close the DTCO loop, the static noise margin and write noise margin sensitivity to cell design parameters and variability in FinFET-based SRAM designs are studied in details.

Modelling RTN and BTI in nanoscale MOSFETs from device to circuit: A review

In this paper we summarize the impact of Statistical Variability (SV) on device performances and study the impact of oxide trapped charges in combination with SV. Traps time constants are described and analysed in combination with SV and time dependent simulations are performed including SV, random traps and charge injection stochasticity. Finally we demonstrate the necessity of statistical simulations in extracting compact models of aged devices and we address the problem of aged SRAM cell reliability.

3-D Statistical Simulation Comparison of Oxide Reliability of Planar MOSFETs and FinFET

New transistor architectures such as fully depleted silicon on insulator (FDSoI) MOSFETs and FinFETs have been introduced in advanced CMOS technology generations to boost performance and to reduce statistical variability (SV). In this paper, the robustness of these architectures to random telegraph noise and bias temperature instability issues is investigated using comprehensive 3-D numerical simulations, and results are compared with those obtained from conventional bulk MOSFETs. Not only the impact of static trapped charges is investigated, but also the charge trapping dynamics are studied to allow device lifetime and failure rate predictions. Our results show that device-to-device variability is barely increased by progressive oxide charge trapping in bulk devices. On the contrary, oxide degradation determines the SV of SoI and FinFET devices. However, the SoI and multigate transistor architectures are shown to be significantly more robust in terms of immunity to time-dependent SV when compared with the conventional bulk device. The comparative study here presented could be of significant importance for reliability resistant CMOS circuits and systems design.

Interplay between statistical reliability and variability: A comprehensive transistor-to-circuit simulation technology

In this paper we present a reliability simulation framework from atomistic simulations up to circuit simulations, including traps interactions with variability sources. Trapping and detrapping dynamics are reproduced by a kinetic Monte-Carlo engine, which enables oxide degradation simulations such as BTI and RTN phenomenon on large ensembles of atomistic devices. Based on these results compact models are extracted and circuit lifetime projections are derived.

Impact of Nonuniform Doping on Random Telegraph Noise in Flash Memory Devices

This paper presents a thorough numerical investigation of the effect of nonuniform doping on random telegraph noise (RTN) in nanoscale Flash memory devices. For a fixed average threshold voltage, the statistical distribution of the RTN fluctuation amplitude is studied with nonconstant doping concentrations in the length, width, or depth direction in the channel, showing that doping increase at the active area corners and retrograde and δ-shape dopings appear as the most promising profiles for RTN suppression. In particular, the improvements offered by retrograde and δ-shape dopings increase the more the high doping regions are pushed far from the channel surface due to a more uniform source-to-drain conduction during read. Finally, the suppression of RTN by engineered doping profiles is correlated with the reduction in cell threshold voltage variability.

Physical Modeling for Programming of TANOS Memories in the Fowler–Nordheim Regime

This paper presents a physics-based model that is able to describe the TANOS memory programming transients in the Fowler-Nordheim uniform tunneling regime across the bottom-oxide layer. The model carefully takes into consideration the trapping/detrapping processes in the nitride, the limited number of traps available for charge storage, and their spatial and energetic distribution. Results are in good agreement with experimental data on TANOS devices with different gate-stack compositions, considering a quite extended range of gate biases and times. The reduced gate-bias sensitivity of the programming transients with respect to the floating-gate cell is explained in terms of a finite number of nitride traps and a thinner extension of the nitride trapping region as the gate bias is increased. The model represents a valid contribution for the investigation of the achievable performances of the TANOS technology.

Accuracy and Issues of the Spectroscopic Analysis of RTN Traps in Nanoscale MOSFETs

This paper investigates the limitations to the accuracy and the main issues of the spectroscopic analyses of random telegraph noise (RTN) traps in nanoscale MOSFETs. First, the impact of the major variability sources affecting decananometer MOSFET performance on both the RTN time constants and the trap depth estimation is studied as a function of the gate overdrive. Results reveal that atomistic doping and metal gate granularity broaden the statistical distribution of the RTN time constants far more than what comes from the random position of the RTN trap in the 3-D device electrostatics, contributing, in turn, to a significant reduction of the accuracy of trap spectroscopy. The accuracy is shown to improve the higher is the gate overdrive, owing to a more uniform and gate-bias-independent surface potential in the channel, with, however, the possible drawback of triggering the simultaneous trap interaction with both the channel and the gate. This simultaneous interaction is, finally, shown to critically compromise trap spectroscopy in thin-oxide devices.

Investigation of the RTN Distribution of Nanoscale MOS Devices From Subthreshold to On-State

This letter presents a numerical investigation of the statistical distribution of the random telegraph noise (RTN) amplitude in nanoscale MOS devices, focusing on the change of its main features when moving from the subthreshold to the on-state conduction regime. Results show that while the distribution can be well approximated by an exponential behavior in subthreshold, large deviations from this behavior appear when moving toward the on-state regime, despite a low probability exponential tail at high RTN amplitudes being preserved. The average value of the distribution is shown to keep an inverse proportionality to channel area, while the slope of the high-amplitude exponential tail changes its dependence on device width, length, and doping when moving from subthreshold to on-state.

Semi-Analytical Model for the Transient Operation of Gate-All-Around Charge-Trap Memories

We present a detailed semi-analytical investigation of the transient dynamics of gate-all-around (GAA) charge-trap memories. To this aim, the Poisson equation is solved in cylindrical coordinates, and a modification of the well-known Fowler-Nordheim formula is proposed for tunneling through cylindrical dielectric layers. Analytical results are validated by experimental data on devices with different gate stack compositions, considering a quite extended range of gate biases and times. Finally, the model is used for a parametric analysis of the GAA cell, highlighting the effect of device curvature on both program/erase and retention.