Louis Gerrer

Modelling RTN and BTI in nanoscale MOSFETs from device to circuit: A review

In this paper we summarize the impact of Statistical Variability (SV) on device performances and study the impact of oxide trapped charges in combination with SV. Traps time constants are described and analysed in combination with SV and time dependent simulations are performed including SV, random traps and charge injection stochasticity. Finally we demonstrate the necessity of statistical simulations in extracting compact models of aged devices and we address the problem of aged SRAM cell reliability.

3-D Statistical Simulation Comparison of Oxide Reliability of Planar MOSFETs and FinFET

New transistor architectures such as fully depleted silicon on insulator (FDSoI) MOSFETs and FinFETs have been introduced in advanced CMOS technology generations to boost performance and to reduce statistical variability (SV). In this paper, the robustness of these architectures to random telegraph noise and bias temperature instability issues is investigated using comprehensive 3-D numerical simulations, and results are compared with those obtained from conventional bulk MOSFETs. Not only the impact of static trapped charges is investigated, but also the charge trapping dynamics are studied to allow device lifetime and failure rate predictions. Our results show that device-to-device variability is barely increased by progressive oxide charge trapping in bulk devices. On the contrary, oxide degradation determines the SV of SoI and FinFET devices. However, the SoI and multigate transistor architectures are shown to be significantly more robust in terms of immunity to time-dependent SV when compared with the conventional bulk device. The comparative study here presented could be of significant importance for reliability resistant CMOS circuits and systems design.

Interplay between statistical reliability and variability: A comprehensive transistor-to-circuit simulation technology

In this paper we present a reliability simulation framework from atomistic simulations up to circuit simulations, including traps interactions with variability sources. Trapping and detrapping dynamics are reproduced by a kinetic Monte-Carlo engine, which enables oxide degradation simulations such as BTI and RTN phenomenon on large ensembles of atomistic devices. Based on these results compact models are extracted and circuit lifetime projections are derived.

Accuracy and Issues of the Spectroscopic Analysis of RTN Traps in Nanoscale MOSFETs

This paper investigates the limitations to the accuracy and the main issues of the spectroscopic analyses of random telegraph noise (RTN) traps in nanoscale MOSFETs. First, the impact of the major variability sources affecting decananometer MOSFET performance on both the RTN time constants and the trap depth estimation is studied as a function of the gate overdrive. Results reveal that atomistic doping and metal gate granularity broaden the statistical distribution of the RTN time constants far more than what comes from the random position of the RTN trap in the 3-D device electrostatics, contributing, in turn, to a significant reduction of the accuracy of trap spectroscopy. The accuracy is shown to improve the higher is the gate overdrive, owing to a more uniform and gate-bias-independent surface potential in the channel, with, however, the possible drawback of triggering the simultaneous trap interaction with both the channel and the gate. This simultaneous interaction is, finally, shown to critically compromise trap spectroscopy in thin-oxide devices.

Investigation of the RTN Distribution of Nanoscale MOS Devices From Subthreshold to On-State

This letter presents a numerical investigation of the statistical distribution of the random telegraph noise (RTN) amplitude in nanoscale MOS devices, focusing on the change of its main features when moving from the subthreshold to the on-state conduction regime. Results show that while the distribution can be well approximated by an exponential behavior in subthreshold, large deviations from this behavior appear when moving toward the on-state regime, despite a low probability exponential tail at high RTN amplitudes being preserved. The average value of the distribution is shown to keep an inverse proportionality to channel area, while the slope of the high-amplitude exponential tail changes its dependence on device width, length, and doping when moving from subthreshold to on-state.

Impact of statistical variability and 3D electrostatics on post-cycling anomalous charge loss in nanoscale Flash memories

This paper presents a detailed simulation investigation of the impact of statistical variability and 3D electrostatics on SILC distribution in nanoscale Flash memories. Considering a 1-TAT model we study the SILC statistics under stationary and dynamic retention conditions. Our results show that SILC is dispersed over the channel area due to non-uniform electrostatics in nanoscale devices. Further, the floating gate poly-silicon granularity plays a major role in determining the SILC distribution, depending on the gate polarity. Dynamic charge loss simulations highlight that the impact of 3D electrostatics is dominant over the cell-to-cell variability. Finally, we analyze the electron emission statistics on a single cell, showing that this gives rise to a lower SILC dispersion than an analytical Poisson charge loss statistics. Our results are fundamental to determine the degree of accuracy of 1D models for the post-cycling charge loss statistics simulation in nanoscale Flash memories.

Statistical Interactions of Multiple Oxide Traps Under BTI Stress of Nanoscale MOSFETs

We report a thorough 3-D simulation study of the correlation between multiple, trapped charges in the gate oxide of nanoscale bulk MOSFETs under bias and temperature instability (BTI). The role of complex electrostatic interactions between the trapped charges in the presence of random dopant fluctuations is evaluated, and their impact on the distribution of the threshold voltage shift and on the distribution of the number of trapped charges is analyzed. The results justify the assumptions of a Poisson distribution of the BTI-induced trapped charges and of the lack of correlation between them, when accounting for time-dependent variability in circuits.

Accurate Simulation of Transistor-Level Variability for the Purposes of TCAD-Based Device-Technology Cooptimization

In this paper we illustrate how the predictive Technology Computer Aided Design (TCAD) process device simulation can be used to evaluate process, statistical, and time-dependent variability at the early stage of the development of new technology. This is critically important for the delivery of accurate early Process Design Kits, including process variability, statistical variability, time-dependent variability (degradation) and their interactions and correlations. This is also critical to the TCAD-based Design-Technology Co-Optimisation (DTCO). To accomplish this task, the fast, large area Coventor virtual fabrication platform SEMulator3D was integrated in the GoldStandradSimulations TCAD-based DTCO tool chain. Published data for Intel 22-nm FinFET technology are used to illustrate and validate the results of the TCAD process and device simulation, the compact model extraction, and the statistical circuit simulation.

Impact of random dopant fluctuations on trap-assisted tunnelling in nanoscale MOSFETs

Abstract In this paper we introduce a novel simulation approach for the analysis of statistical variability in the trap-assisted tunnelling (TAT) gate leakage current in ultra-scaled MOSFETs. It accounts for the stochastic nature of trapping/emission dynamics underlying TAT current, and enables the simulation of TAT in the time domain. We demonstrate that random dopant fluctuations induce significant variability in the TAT gate leakage and investigate the details of its origin. Finally we present TAT current characteristics for different dopants configurations.

Interplay Between Statistical Variability and Reliability in Contemporary pMOSFETs: Measurements Versus Simulations

This paper presents an extensive study of the interplay between as-fabricated (time-zero) variability and gate oxide reliability (time-dependent variability) in contemporary pMOSFETs. We compare physical simulation results using the atomistic simulator GARAND with experimental measurements. The TCAD simulations are accurately calibrated to reproduce the average transistor behavior. When random discrete dopants, line edge roughness, and gate polysilicon granularity are considered, the simulations accurately reproduce time-zero (as-fabricated) statistical variability, as well as time-dependent variability data, represented by threshold voltage shift distributions. The calibrated simulations are then used to predict the reliability behavior at different bias conditions and for different device dimensions.