Reiko Nojima

Synergistic power/area optimization with transistor sizing and wire length minimization [CMOS logic]

The paper proposes a method to realize low-power control-logic modules by combining transistor-size optimization and transistor layout. When applied to a circuit with 10,000 transistors, the optimizer has reduced the average transistor size to one eighth while maintaining the same delay. The power dissipation is cut to half even when wiring capacitances are dominant.

Power and area optimization by reorganizing CMOS complex gate circuits

Thispaper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor layout. Complex gate reorganization minimizes transistor count and net count without changing the functionality of the circuit. Transistor sizing and layout are interdependent, the optimization of one results in the optimization of the other. The authors applied the reorganization method to a 2400-transistor circuit, and succeeded in reducing the transistor count by 12%, and the net count by 13%. Transistor sizing and layout compaction reduced the average transistor size by one eighth, while the same delay was maintained. Power dissipation was cut to less than half, even when wiring capacitances were dominant.