Takashi Mitsuhashi

Switching activity analysis using Boolean approximation method

This paper presents a novel algorithm to estimate the signal probability and switching activity at all nodes in a combinational logic circuit under a zero-delay model without constructing global BDDs. By using Taylor expansion technique, the first-order signal correlation effects due to reconvergent fan-out nodes are taken into account. High accuracy is achieved by considering the dependency of the signal probability and switching activity on each primary input. High speed is also achieved by using the incremental approach for probability calculation. Our approach is able to handle large circuits, since it does not need to construct global BDDs for the probability calculation. The analysis of the time complexity and the experimental results show the running time of our approach to be about 100 times shorter than that of the most accurate approach previously proposed and that our approach has comparable accuracy. The error of the total power estimation is about 0.5% on average.

A Resistance Calculation Algorithm and Its Application to Circuit Extraction

This paper describes a resistance calculation program for a layout verification system called EMAP. A new resistance calculation algorithm, based on the finite-element method, and a generalized resistor model, used in this program, are discussed. Contact resistance effects, pinch resistors, and other kinds of resistance appearing in LSIs are considered in the proposed model. The proposed two-dimensional model, in which an inherent three-dimensional structure of resistors is embedded, allows efficient and accurate resistance calculation. The resistance value for an arbitrarily shaped multiregional resistivity and multiport resistor can be calculated efficiently by the proposed algorithm. The algorithm, called direct admittance matrix derivation, makes it possible to eliminate the tedious boundary condition treatment, and provides efficient matrix manipulation. Implementation techniques and related algorithms are discussed; these include resistor recognition from mask artwork, mesh generation for finite elements, node numbering for matrix bandwidth reduction, some properties of matrices appearing in the proposed algorithm, and a circuit representation method for the derived matrices. Some implementation results are also discussed.

An Integrated Mask Artwork Analysis System

A new LSI artwork analysis and processing system, called EMAP, is described with algorithms, a database schema and applications. EMAP provides the designer with the artwork verification and processing tools which include mask artwork processing, geometrical design rule checking, connectivity analysis and electrical circuit parameter calculation. The circuit connectivity data derived from the mask artwork data is used for input to a logic simulator, a timing simulator, a circuit simulator and a circuit schematic generator.

A clock-gating method for low-power LSI design

This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed gated-clock tree synthesizer for the first issue, and timing constraints generator and clock delay estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts.

A layout checking system for large scale integrated circuits

This paper describes a new design rule checking system for LSI mask patterns. Major features of the system are a relatively small computing time needed, even for very large circuits (e.g. 10,000 elements), wide applications to a variety of fabrication processes, due to its functional flexibility, and minimized spurious errors.

Programs for Verifying Circuit Connectivity of MOS/LSI Mask Artwork

This paper describes three programs which perform connectivity rule check, logic gate recognition for logic simulation and circuit connectivity comparison. These programs have been developed for verifying circuit connectivity extracted from mask artwork. Powerful algorithms are used in these programs, including a heuristic graph comparison algorithm, to realize highly practical verification aids. Through the combined use of these programs, more cost-effective verification is possible.

Layout driven re-synthesis for low power consumption LSIs

A new technology re-mapping method named LDR (LayoutDriven Re-synthesis), which is applied after placement, is proposed.LDR executes re-mapping and re-placement simultaneouslyin order to minimize power consumption with placementinformation.High switching activity nets are concealed insidethe re-mapped cells or are shortened by re-placement in LDR.To estimate power consumption, LDR uses static power estimatorfor combinational circuits.LDR also calculates wirecapacitances accurately based on placement information toevaluate power.Experimental results show that 20% powerreduction compared with original circuits is performed by proposed method.

Switching activity analysis for sequential circuits using Boolean approximation method

We propose an incremental probabilistic approach to calculate the signal probabilities and switching activities of the internal nodes of sequential logic circuits. Spatio-temporal correlations are fully considered by using Multi-Terminal Binary Decision Diagrams (MTBDD) with real number valued terminals. The running time of our approach is short because the depth of the MTBDD does not depend on circuit size but only on the user-specified unrolling number, which is usually 2 or 3. Experimental results show that our approach is 100-times faster than logic simulation and 10-times more accurate than the previous approach which ignores all correlations.

Fanout-tree restructuring algorithm for post-placement timing optimization

This paper proposes a fanout-tree restructuring algorithm for post-placement timing optimization to meet timing constraints. The proposed algorithm restructures a fanout-tree by finding a tree in a graph which represents a multi-terminal net, and inserts buffer cells and resizes cells based on an accurate interconnection RC delay without degrading routability. The algorithm has been implemented and applied to a number of layout data generated by timing driven placement. Application results show a 17% reduction in circuit delay on the average.

An effective data structure for VLSI layout systems

An effective data structure is presented which is called a B-2 tree (bucket tree with 2-D binary trees) suitable for VLSI layout systems. The B-2 tree consists of a main binary tree which forms a directory for buckets, and bisector lists with 2-D binary trees. Experimental results have shown that the B-2 tree is superior to other data structures in region search performance even for huge size data. It has also been shown that its region search performance is not influenced by the distribution of objects on a chip.<<ETX>>