Masami Murakata

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling

A single-chip H.264 and MPEG-4 audio-visual LSI for mobile applications including terrestrial digital broadcasting system (ISDB-T / DVB-H) with a module-wise, dynamic voltage/frequency scaling architecture is presented for the first time. This LSI can keep operating even during the voltage/frequency transition, so there is no performance overhead. It is realized through a dynamic deskewing system and an on-chip voltage regulator with slew rate control. By the combination with traditional low power techniques such as embedded DRAM and clock gating, it consumes only 63 mW in decoding QVGA H.264 video at 15 frames/sec and MPEG-4 AAC LC audio simultaneously.

A clock-gating method for low-power LSI design

This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed gated-clock tree synthesizer for the first issue, and timing constraints generator and clock delay estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts.

Increasing minimum operating voltage (V DDmin ) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators

In order to explore the feasibility of the large scale subthreshold logic circuits and to clarify the lower limit of supply voltage (VDD) for logic circuits, the dependence of minimum operating voltage (VDDmin) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90-nm CMOS ring oscillators (ROs). The measured average VDDmin of inverter ROs increased from 90 mV to 343 mV when the number of RO stages increased from 11 to 1 Mega, which indicates the difficulty of the VDD scaling in the large scale subthreshold logic circuits. The dependence of VDDmin on the number of stages is calculated with the subthreshold current model with random threshold voltage (VTH) variations and compared with the measured results, which confirm the tendency of the measurement.

Layout driven re-synthesis for low power consumption LSIs

A new technology re-mapping method named LDR (LayoutDriven Re-synthesis), which is applied after placement, is proposed.LDR executes re-mapping and re-placement simultaneouslyin order to minimize power consumption with placementinformation.High switching activity nets are concealed insidethe re-mapped cells or are shortened by re-placement in LDR.To estimate power consumption, LDR uses static power estimatorfor combinational circuits.LDR also calculates wirecapacitances accurately based on placement information toevaluate power.Experimental results show that 20% powerreduction compared with original circuits is performed by proposed method.

Switching activity analysis for sequential circuits using Boolean approximation method

We propose an incremental probabilistic approach to calculate the signal probabilities and switching activities of the internal nodes of sequential logic circuits. Spatio-temporal correlations are fully considered by using Multi-Terminal Binary Decision Diagrams (MTBDD) with real number valued terminals. The running time of our approach is short because the depth of the MTBDD does not depend on circuit size but only on the user-specified unrolling number, which is usually 2 or 3. Experimental results show that our approach is 100-times faster than logic simulation and 10-times more accurate than the previous approach which ignores all correlations.

Fanout-tree restructuring algorithm for post-placement timing optimization

This paper proposes a fanout-tree restructuring algorithm for post-placement timing optimization to meet timing constraints. The proposed algorithm restructures a fanout-tree by finding a tree in a graph which represents a multi-terminal net, and inserts buffer cells and resizes cells based on an accurate interconnection RC delay without degrading routability. The algorithm has been implemented and applied to a number of layout data generated by timing driven placement. Application results show a 17% reduction in circuit delay on the average.

Concurrent logic and layout design system for high performance LSIs

This paper presents a concurrent logic and layout design system for high performance LSIs. This system precisely estimates interconnection delays considering physical information in logic design stage. Precise interconnection delay estimation makes iteration free designs possible. Application results show that this system realized high performance LSIs over 100 MHz without logic-layout design iteration.

Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI

The module-wise dynamic voltage and frequency scaling (MDVFS) scheme is applied to a single-chip H.264/MPEG-4 audio/visual codec LSI. The power consumption of the target module with controlled supply voltage and frequency is reduced by 40% in comparison with the operation without voltage or frequency scaling. The consumed power of the chip is 63 mW in decoding QVGA H.264 video at 15 fps and MPEG-4 AAC LC audio simultaneously. This LSI keep operating continuously even during the voltage transition of the target module by introducing the newly developed dynamic de-skewing system (DDS) which watches and control the clock edge of the target module.

Physical design CAD in deep sub-micron era

We investigate the impacts of miniaturization of device dimensions that causes a paradigm shift in LSI design methodology. Major design issues in deep sub micron LSIs, namely, wire delay, circuit complexity and power consumption are discussed based on scaling theory. To resolve these issues, a concept called layout driven synthesis and optimization Is introduced. Based on this concept, EDA programs including circuit optimizer, clock tree synthesis, technology mappers and so on, have been developed. Timing optimization and power minimization methods using the concept are discussed in detail. Evaluation results obtained by proposed approach show superior performance and dramatic reduction of design period, and indicate validity of layout driven synthesis and optimization concept.

A DRAM module generator with an expandable cell array scheme

This paper describes a DRAM module generator (DRAMGen) with an expandable cell array scheme. DRAMGen uses a modularization scheme. This expandable cell array scheme uses the cell array segment as the unit of increment and applies shared sense-amplifier scheme. This scheme reduces the area penalty to less than five percent and has little performance penalty. Using a 0.35 /spl mu/m process technology, a series of DRAM macros with flexible bank, row, column, and I/O-bit configurations consequently produce 2112 derivatives. The module generator has successfully generated a number of macros, taking five seconds for each macro, including a 32 Mb macro with a 150 MHz cycle time.