Reiner Leihkauf

Functional IC analysis through chip backside with nano scale resolution - E-beam probing in FIB trenches to STI level

Successful measurements, applying the EBP to the backside of thinned circuitry, using test structures and commercial chips have been demonstrated. In addition to the well known CCVC a new contrast mechanism named space charge coupled voltage contrast (SCCVC) was detected, which strongly increased the EBP signal measured directly on the transistor source or drain regions. Therefore, measurements are possible as long as the electron beam can be placed on a transistor well area, which is larger than the lower metal lines by a factor of 3. The voltage signal has been produced correctly with 100mV noise margin on one of the test structures and since the coplanarity of the trench bottom to silicon surface is excellent, the same accuracy can be expected for any DUT when the process is properly calibrated. As a result, the presented method is very promising since the lateral resolution potential of an EBP system is only limited by the low energy E-beam diameter. Improvements in this field have not been used to enhance EBP in recent years but even with the present systems, measurements on sub-50nm technology seem to be possible. Furthermore, optical methods are struggling with their resolution limits and therefore backside EBP can become a very powerful method in the near future.

Physical analysis, trimming and editing of nanoscale IC function with backside FIB processing

Abstract Most well established IR-beam based failure analysis techniques and also conventional circuit edit procedures are facing severe challenges resulting from the aggressive downscaling of today’s IC technology. To allow for alternative strategies, novel CE and functional chip analysis techniques have been developed, all being based on backside FIB processing. Additionally, in depth characterization of FIB induced device alterations has shown that a >20% speed gain can be achieved with the proposed FIB thinning procedure. In contrast to all known techniques, this offers trimming of chip internal timing conditions on fully functional samples without being bound to pre-planned fuses or varactors. Based on various experimental results and physical device simulations, this paper briefly reviews the necessary FIB process for which the main focus lies on the FIB induced device alteration. Finally, the novel CE and analysis techniques will be discussed regarding their fields of application, benefits compared to established techniques and theoretical limitations.

Backside E-Beam Probing on Nano scale devices

IC debug with E-beam probing is presented in an innovative application accessing the active device directly from chip backside after FIB preparation. The potential of this approach in nanoscale and gigahertz dimensions is evaluated.

Distinction of Photo-Electric and Thermal Effects in a MOSFET by 1064 nm Laser Stimulation

Thermal (TLS) and photoelectric (PLS) laser stimulation techniques are now widely used in failure analysis of integrated circuits. The stimulation signatures when using a 1064 nm laser are often a combination of PLS and TLS. This work presents a quantitative investigation of 1064 nm laser stimulation effects on single NMOSFET devices that isolates the two contributors. The results support the basic understanding of the static and dynamic device behavior when stimulated by 1064nm laser

Novel Flip-Chip Probing Methodology Using Electron Beam Probing

The measurement of timing and voltage signals inside integrated circuits (IC) is critical to debugging new devices, to failure analysis of advanced devices, validating new IP (intellectual property) in new silicon, etc. E-beam probing (EBP) has been very useful for front side devices for over two decades. For measuring signals below the top metal layers, probe pads are made using a focused ion beam (FIB) where lower metal was accessible. Increasing migration of ICs to flip chip packaging has necessitated the need for a new tool set or methodology for design debug and failure analysis. This paper introduces data taken from a flip chip using an IDS 10K+ E-beam Prober (EBPr). The samples are thinned using an Allied HiTech polishing wheel and the Credence OptiFIB. The investigation utilized the capability of the EBPr to acquire both repeating (clocks) and non-repeating signals at various: supply voltages, loop lengths frequencies.