Uwe Kerst

Quantitative Investigation of Laser Beam Modulation in Electrically Active Devices as Used in Laser Voltage Probing

Among the backside analysis techniques of integrated circuits, laser voltage probing provides signal levels of the nodes. In the past, signal interpretation has been empirically based. In this paper, for the first time, an in-depth investigation of signal origin and parametric measurements of active devices have been performed, and a concise physical model of laser beam absorption has been developed. In the laser measurements, switching metal-oxide-semiconductor field-effect transistors and their basic components - reverse-biased diodes and gates in inversion - have been studied parametrically. The results show the ranges and limits of linear signal-to-voltage correlation and match the model successfully.

Investigation of Laser Voltage Probing Signals in CMOS Transistors

The increasing number of interconnection layers is making failure analysis of integrated circuits (ICs) increasingly complex. In addition, the decreasing supply voltage is a challenge for failure analysis equipment, as minimum detection levels are reached. Laser voltage probing (LVP) is a common method for probing internal nodes through the silicon back side, and is particularly suited to low-voltage measurements. However, to date there has been little work on detailed understanding of the physical origin of LVP signals. This article presents measurements of LVP signal strength on large test structures over a wide range of parameters as a first approach to detailed understanding of LVP physics and future scaling. All the measurements we present were performed using a continuous-wave 1319 nm laser. In addition to the usual time-domain LVP measurements, the authors demonstrate rapid data acquisition scheme using frequency-domain measurements. This method allows rapid voltage sweeps and also allows for (x, y) mapping of signal strength across device structures. The signal strengths are in accord with qualitative models.

Physical Techniques for Chip-Backside IC Debug in Nanotechnologies

Physical failure analysis remains indispensable for final defect confirmation, but is increasingly difficult due to semiconductor technology advances with smaller feature sizes, many metal layers, and flip-chip packaging. This article reports on how, despite an uphill battle, constant innovations keep physical failure analysis going.

Impact of back side circuit edit on active device performance in bulk silicon ICs

Parallel thinning of silicon, close to active devices, is a risk potential specific to back side editing. Monitored FETs and ring oscillators showed no significant performance change for various remaining silicon thicknesses down to SOI-like structures

Security Risks Posed by Modern IC Debug and Diagnosis Tools

Silicon debug and diagnosis (SDD) has successfully combined recent developments of IC Failure Analysis (FA) techniques in order to have local physical interaction with the circuit function down to nano scale. These techniques, mainly optical interactions applied through chip backside, are assisted by a revolutionary Focused Ion Beam (FIB) backside preparation technique that keeps the chip fully functional while leaving sub micron thickness of Si substrate on an area large enough to call it semi-global. With such a treatment, any physical interaction, even electrical probing to any node, is possible through chip backside. On top of that, the performance of the devices can be modulated in situ with this FIB process. All these FA and SDD innovations open up a new world of hardware attack processes, accessible in FA labs world wide on an hourly basis, that security sensitive ICs need to be protected against.

Conduction and material transport phenomena of degradation in electrically stressed ultra low-k dielectric before breakdown

The electrical degradation of ultra low-k SiCOH dielectric before breakdown is investigated. A new technique to obtain information before breakdown has been developed to define stress conditions and observe degradation patterns before total destruction occurs. Electrical measurements and physical inspection in specifically designed test structures have been made to focus on intrinsic properties. A typical leakage current characteristic, voiding and tantalum transport have been observed. These observations have been interpreted by quantitatively adapting physical effects. This investigation provides a model that describes the observed phenomena in a qualitatively manner.

Functional IC analysis through chip backside with nano scale resolution - E-beam probing in FIB trenches to STI level

Successful measurements, applying the EBP to the backside of thinned circuitry, using test structures and commercial chips have been demonstrated. In addition to the well known CCVC a new contrast mechanism named space charge coupled voltage contrast (SCCVC) was detected, which strongly increased the EBP signal measured directly on the transistor source or drain regions. Therefore, measurements are possible as long as the electron beam can be placed on a transistor well area, which is larger than the lower metal lines by a factor of 3. The voltage signal has been produced correctly with 100mV noise margin on one of the test structures and since the coplanarity of the trench bottom to silicon surface is excellent, the same accuracy can be expected for any DUT when the process is properly calibrated. As a result, the presented method is very promising since the lateral resolution potential of an EBP system is only limited by the low energy E-beam diameter. Improvements in this field have not been used to enhance EBP in recent years but even with the present systems, measurements on sub-50nm technology seem to be possible. Furthermore, optical methods are struggling with their resolution limits and therefore backside EBP can become a very powerful method in the near future.

Physical analysis, trimming and editing of nanoscale IC function with backside FIB processing

Abstract Most well established IR-beam based failure analysis techniques and also conventional circuit edit procedures are facing severe challenges resulting from the aggressive downscaling of today’s IC technology. To allow for alternative strategies, novel CE and functional chip analysis techniques have been developed, all being based on backside FIB processing. Additionally, in depth characterization of FIB induced device alterations has shown that a >20% speed gain can be achieved with the proposed FIB thinning procedure. In contrast to all known techniques, this offers trimming of chip internal timing conditions on fully functional samples without being bound to pre-planned fuses or varactors. Based on various experimental results and physical device simulations, this paper briefly reviews the necessary FIB process for which the main focus lies on the FIB induced device alteration. Finally, the novel CE and analysis techniques will be discussed regarding their fields of application, benefits compared to established techniques and theoretical limitations.

Backside E-Beam Probing on Nano scale devices

IC debug with E-beam probing is presented in an innovative application accessing the active device directly from chip backside after FIB preparation. The potential of this approach in nanoscale and gigahertz dimensions is evaluated.

Non destructive 3D chip inspection with nano scale potential by use of backside FIB and backscattered electron microscopy

Three dimensional chip inspection with sub micron resolution is essential for physical failure analysis. The established approaches often require cross sections, destroying the device under test. This paper presents a non destructive way to gain precise geometrical information of the transistor- and metal-one-layer with the use of state of the art backside FIB preparation and backscattered electron microscopy.