Rudolf Schlangen

Non-destructive defect depth determination at fully packaged and stacked die devices using Lock-in Thermography

This paper will present a new non-destructive approach for the 3D localization of thermally active buried defects in single chip and stacked die architectures by use of Lock-in Thermography (LIT). The basic principles concerning the thermal wave propagation through different material layers and the resulting phase shift will be presented and discussed. Based on that, the LIT application for 3D defect localization will be evaluated at both fully packaged single chip and stacked die devices by comparing theoretical and experimental data.

Physical Techniques for Chip-Backside IC Debug in Nanotechnologies

Physical failure analysis remains indispensable for final defect confirmation, but is increasingly difficult due to semiconductor technology advances with smaller feature sizes, many metal layers, and flip-chip packaging. This article reports on how, despite an uphill battle, constant innovations keep physical failure analysis going.

Dynamic lock-in thermography for operation mode-dependent thermally active fault localization

Microscopic Lock-In Thermography (LIT) has proven unsurpassed capability for non-destructive localization of thermally active defects like shorts or resistive opens, even through the full package. This paper briefly reviews the real-time pixel-wise lock-in methodology, as the key to the extreme temperature sensitivity. A typical LIT work-flow is demonstrated whereby the main focus of the paper is to discuss and demonstrate different ways how to activate the thermally active defects with more complex DUTs/defect signatures, requiring ATE docking.

Impact of back side circuit edit on active device performance in bulk silicon ICs

Parallel thinning of silicon, close to active devices, is a risk potential specific to back side editing. Monitored FETs and ring oscillators showed no significant performance change for various remaining silicon thicknesses down to SOI-like structures

Functional IC analysis through chip backside with nano scale resolution - E-beam probing in FIB trenches to STI level

Successful measurements, applying the EBP to the backside of thinned circuitry, using test structures and commercial chips have been demonstrated. In addition to the well known CCVC a new contrast mechanism named space charge coupled voltage contrast (SCCVC) was detected, which strongly increased the EBP signal measured directly on the transistor source or drain regions. Therefore, measurements are possible as long as the electron beam can be placed on a transistor well area, which is larger than the lower metal lines by a factor of 3. The voltage signal has been produced correctly with 100mV noise margin on one of the test structures and since the coplanarity of the trench bottom to silicon surface is excellent, the same accuracy can be expected for any DUT when the process is properly calibrated. As a result, the presented method is very promising since the lateral resolution potential of an EBP system is only limited by the low energy E-beam diameter. Improvements in this field have not been used to enhance EBP in recent years but even with the present systems, measurements on sub-50nm technology seem to be possible. Furthermore, optical methods are struggling with their resolution limits and therefore backside EBP can become a very powerful method in the near future.

Physical analysis, trimming and editing of nanoscale IC function with backside FIB processing

Abstract Most well established IR-beam based failure analysis techniques and also conventional circuit edit procedures are facing severe challenges resulting from the aggressive downscaling of today’s IC technology. To allow for alternative strategies, novel CE and functional chip analysis techniques have been developed, all being based on backside FIB processing. Additionally, in depth characterization of FIB induced device alterations has shown that a >20% speed gain can be achieved with the proposed FIB thinning procedure. In contrast to all known techniques, this offers trimming of chip internal timing conditions on fully functional samples without being bound to pre-planned fuses or varactors. Based on various experimental results and physical device simulations, this paper briefly reviews the necessary FIB process for which the main focus lies on the FIB induced device alteration. Finally, the novel CE and analysis techniques will be discussed regarding their fields of application, benefits compared to established techniques and theoretical limitations.

Backside E-Beam Probing on Nano scale devices

IC debug with E-beam probing is presented in an innovative application accessing the active device directly from chip backside after FIB preparation. The potential of this approach in nanoscale and gigahertz dimensions is evaluated.

Non destructive 3D chip inspection with nano scale potential by use of backside FIB and backscattered electron microscopy

Three dimensional chip inspection with sub micron resolution is essential for physical failure analysis. The established approaches often require cross sections, destroying the device under test. This paper presents a non destructive way to gain precise geometrical information of the transistor- and metal-one-layer with the use of state of the art backside FIB preparation and backscattered electron microscopy.

Contact to contacts or silicide by use of backside FIB circuit edit allowing to approach every active circuit node

Abstract Direct measurements, connecting to central circuit nodes without changing the performance of the circuitry are critical in modern FA but often impossible for recent IC technologies. This paper shows two new methods based on FIB backside circuit edit, allowing to reach every circuit node existing on front-end level.

RF performance increase allowing IC timing adjustments by use of backside FIB processing

Dealing with timing related soft fails has become predominant with recent technologies and is expected more so future. A backside FIB edit procedure allowed trimming of internal timing conditions, with demonstrated FIB-induced speed enhancement ≫ 20%. This proposed technique seems applicable to any on chip circuitry, expanding rapid prototyping options.