Richard A. Bailey

Reliability properties of low-voltage ferroelectric capacitors and memory arrays

We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-nm CMOS logic process with 5LM Cu/FSG. Low voltage (<1.5 V) operation is enabled by the 70-nm thick MOCVD PZT ferroelectric films. Data loss resulting from high temperature bakes is primarily caused by the imprint effect, which shows /spl sim/1.5 eV time-to-fail activation energy. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 10/sup 13/ write/read polarization switching cycles. Retention measured after 10/sup 12/ switching cycles demonstrates no degradation relative to arrays with minimal cycling.

Reliability Demonstration of a Ferroelectric Random Access Memory Embedded within a 130nm CMOS Process

Reliable operation of a 4 Mb ferroelectric random access memory (FRAM) embedded within a standard 130 nm CMOS process is demonstrated. Intrinsic endurance test to 5.4×1012 cycles shows no degradation of switched polarization. 10 year, 85degC, data retention life is demonstrated with 125°C data bake to 1,000 Hrs with no fails.

High Temperature Data Retention of Ferroelectric Memory on 130nm and 180nm CMOS

Systematic evaluation of ferroelectric memory (FRAM) data retention mechanisms under high temperature exposure are reported. The FRAM devices are embedded on ultra-low power, analog-enhanced 130nm and 180nm CMOS technologies. Capability of the FRAM to retain data through 260°C Pb-free solder assembly reflow is demonstrated. The 130nm FRAM is shown to achieve the equivalent of 10 years data retention at 125°C, with intrinsic margin comparable to the 180nm FRAM, previously shown to achieve 10 years at 125°C retention.