John A. Rodriguez

An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at V DD =0V with <400ns wakeup and sleep transitions

We demonstrate a non-volatile logic (NVL)-based SoC that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400ns to restore the system state upon power-up. Without NVL, a chip would either have to keep all flip-flops powered resulting in high standby power, or waste energy and time rebooting after power-up. For energy harvesting applications, NVL is a “must have” because there is no constant power source available to keep flip-flops (FFs) alive, and even when the intermittent power source is available, boot-up code alone may consume all of the harvested energy. For handheld devices with limited cooling and battery capacity, zero-leakage ICs with “instant-on” capability are ideal.

An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at

This paper presents a nonvolatile logic (NVL)-based 32-b microcontroller system-on-chip (SoC) that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400 ns to restore the system state upon power-up. Nonvolatile Fe-Cap-based mini-arrays backup the machine state and allow the chip to wake up instantly after a power cycle. Without NVL, a chip would either have to keep all flip-flops powered, resulting in high standby power, or waste energy and time rebooting after power-up. NVL allows systems to use leakier processes to achieve higher performance/lower dynamic power while still having zero leakage in the sleep mode. Optimized system, architecture, and circuit techniques are presented that make NVL practical by adding only 3.6% to the SoC area. Since nonvolatile elements are added to the SoC, reliability and testability have to be key features of the design. This is the first NVL SoC with measured NVL bitcell read signal margin data and extensive test and debug capabilities. The chip is fabricated in a commercial 130-nm low-leakage process and uses a single 1.5-V power supply.

{\rm VDD}=

(Pb,Zr)TiO3 (PZT) films have been prepared by metal organic chemical vapor deposition on 200mm wafers. Phase pure perovskite films were deposited in a self-correcting region where the Pb stoichiometry is relatively insensitive to increasing Pb content in the gas phase. Films deposited with Pb flows lower than those used in the self-correcting region showed second phase ZrO2 whereas films deposited at Pb flows higher than those used in the self-correcting region showed second phase PbO. The PZT grains are columnar, extending from the bottom electrode to the top electrode. In the self-correcting region, PZT films of 70nm nominal thickness show good ferroelectric behavior with switched polarization of ∼40μC∕cm2 at 1.5V and saturation voltage of ∼1.2V. The films have an average roughness of ∼4nm with grain size of ∼700A. The impact of the deposition parameters such as deposition temperature, pressure, precursor flow, and oxygen flow during deposition on the self-correcting region was investigated. Increasing ...

0 V Achieving Zero Leakage With

We report experimental investigations of externally applied mechanical stress on 70 nm Pb(Zr,Ti)O3 ferroelectric capacitors embedded within a 130 nm complementary metal-oxide-semiconductor manufacturing process. An average increase in the remnant polarization of 3.37% per 100 MPa compressive uniaxial stress was observed. The maximum polarization increased by 2.68% per 100 MPa, while the cycling endurance was not affected by stress. The significant difference between experiment and the lattice distortion model suggests that two mechanisms are responsible for the polarization change. These results indicate that stress engineering may be used to enhance the signal margin in ferroelectric random access memory and enable technology scaling.

{ 400-ns Wakeup Time for ULP Applications

Ferroelectric materials are the most common example of a Landau structure, defined as a system having an atom/mass moving in a double-well energy landscape. These materials have applications in memories, actuators, low power logic transistors, and so on. For a bipolar ac signal typical in most of the applications, one suspects that the repeated roller coaster shuttling of the moving atoms located microscopically at the domain walls could lead to bond dissociation, suggesting a new channel for defect generation with no classical counterpart. Here, we demonstrate that once the bipolar pulses initiate transfer of atoms between the energy pockets, the transient overshoot away from their equilibrium positions (hot atoms) leads to significant increase in defect generation. We interpret the degradation theoretically and demonstrate a set of soft-switching schemes to control the hot atom damage and to improve the device lifetime dramatically. The damage mechanism should be generic in other Landau structures, such as microelectromechanical systems, nonvolatile memories, and analogous control strategies should improve the lifetime of all such bistable devices.

Stoichiometry and phase purity of Pb(Zr,Ti)O3 thin films deposited by metal organic chemical vapor deposition

Systematic evaluation of ferroelectric memory (FRAM) data retention mechanisms under high temperature exposure are reported. The FRAM devices are embedded on ultra-low power, analog-enhanced 130nm and 180nm CMOS technologies. Capability of the FRAM to retain data through 260°C Pb-free solder assembly reflow is demonstrated. The 130nm FRAM is shown to achieve the equivalent of 10 years data retention at 125°C, with intrinsic margin comparable to the 180nm FRAM, previously shown to achieve 10 years at 125°C retention.