Christine Hau-Riege

A study of wafer level package board level reliability

Board level reliability studies have been performed on wafer level packages (WLP) with various solder ball alloys, underbump metallurgy compositions, and redistribution (RDL) metal thicknesses. All of the WLPs studied pass drop shock with the thicker RDL having the best performance. In contrast to drop shock, thicker RDL did not significantly improve thermal cycle on board reliability. A WLP with no underbump metallurgy (UBM) passed drop shock, but the temperature cycle performance was marginal. A WLP with Ni-doped alloy and NiCu UBM passed drop shock; however, this Ni-rich joint failed temperature cycle.

Electromigration of solder balls for wafer-level packaging with different under bump metallurgy and redistribution layer thickness

Electromigration (EM) has been conducted on lead-free solder balls in wafer-level packages for different redistribution layer (RDL) thicknesses, under bump metallurgy (UBM) schemes, and lead-free solder alloys. Two different types of EM-induced voids were observed at the electron-source side: pancake void between the solder/RDL interface and through-thickness voids in the RDL. In both cases, voids formed at the interface of CuSn intermetallic compound and solder. A Ni-layer in the UBM was found to prolong EM lifetime by slowing the diffusion of Sn into the Cu RDL relative to a Cu-only UBM. The absence of UBM led to the shortest EM lifetime due to direct contact of solder to RDL. Also, a thicker RDL extended lifetime proportionately to the decrease in current density and Joule heating at the critical interface. On the other hand, adding Ni and Ge to the SAC alloy did not statistically impact lifetime.

The impact of different under bump metallurgies and redistribution layers on the electromigration of solder balls for wafer-level packaging

Electromigration performance has been characterized for lead-free solder balls in wafer-level packaging for different solder metallurgy, under bump metallurgy thickness, and redistribution layer thickness and composition. The electromigration lifetimes in this study were found to strongly correlate with the thickness of under bump metallurgy as well as redistribution layer, spanning more than an order-of-magnitude in median time to failure. Also, a redistribution layer comprising of a Ni/Cu bilayer led to a significant lifetime improvement over its Cu-only counterpart, while a change in solder composition did not affect lifetime. Through extensive failure analysis, the differences in lifetimes can be linked to the amount CuSn formation as determined by the under bump metallurgy thickness as well as the location of the CuSn formation as determined by the redistribution layer thickness. Finally, activation energy has been characterized for a process leg with Cu redistribution layer and under bump metallurgy to be 1.34eV, and a current density exponent to be 3.8.

Electromigration characterization of lead-free flip-chip bumps for 45nm technology node

We have conducted electromigration experiments on lead-free SnAg flip-chip bump interconnection for 45nm technology node. We report lifetime distributions, kinetic parameters and intermetallic compound formation. Further, we discuss the impact of Ag-concentration as well as current direction on the electromigration reliability of these flip-chip bumps. Based on these analyses, we conclude that lead-free bumps lead to significantly more robust electromigration reliability than their SnPb counterparts, which render lead-free bumps a suitable replacement for the present and future technology nodes in terms of their current-carrying capability.

Requirement of effective fabless/foundry interactions for achieving robust product reliability

It is no longer sufficient for foundries to provide only process technology qualification data (for example, device hot carrier, TDDB, BTI, interconnect EM, SM etc.) to the fabless companies as it has been done traditionally. At the nanometer scale, process variations (die to die & within die) coupled with shrinking reliability margins have significantly reduced the design space while circuit designs become increasingly complicated. Foundries need to provide detailed reliability information to enable process-variability & reliability-aware designs that allow the fabless users to leverage the benefits of the advanced technologies. The information is needed for all users and is critical to be available in the process development phase for early technology adaptors. Information should include detailed reliability design rules/tools in form of device/interconnect degradation models that incorporate statistical/process variations. These models/tools can help designers to identify and to mitigate circuit reliability risks in the early design phase. This paper addresses this shift of paradigm that allows fabless designs to keep pace with the rapidly changing nano scale technologies.

A study of self- and mutual-heating in wafer level packaging systems

A detailed investigation of the self- and mutual-heating of todays wafer level packaging system has been characterized in terms of the ambient temperature, air flow, and presence of Cu planes in the board and an attached die. For self-heating measurements, interconnects in the board and die were individually powered. For mutual-heating measurements, the traces in the board were simultaneously powered, a trace and die were powered, or all traces and die were powered. Of these effects, mutual-heating at product-like conditions led to the largest temperature rise, while ambient temperature, fan on or off, and passive die led to less impact. The presence of Cu planes in the board led to large increases in thermal dissipation thus reducing temperature rise by about half for all scenarios. The results from this study were compared to a long-standing industry specification for a common condition, for which large margins were observed in the measured results. Therefore, an explicit thermal study of wafer-level packaging system can alleviate design constraints and improve thermal management.

Key metrics for the electromigration performance for solder and copper-based package interconnects

This paper presents electromigration results over a wide spectrum of far backend interconnects, including microbump, copper pillar, thermal compression flip chip bump, lead free bump and solder ball, in order to rank their performances and identify key metrics for robust electromigration reliability. A compilation of results show two regimes of performance, or current-density-carrying capability, according to the structures solder-to-Cu ratio. That is, relatively low performance was measured for structures with solder-to-Cu ratios higher than 3 such as solder balls, lead-free bumps, and Cu pillars on narrow trace. Here, to local Cu is consumed by CuSn formation, and voids formed along the interface of the CuSn and solder in the bump or ball, or in the cathode trace connection. Relatively high performance was measured for structures with solder-to-Cu ratios less than 3 such as Cu pillars and TCFC bumps on wider traces or pads as well as microbump. Here, the Cu connection remains intact despite CuSn formation. A steady-state or near steady-state situation develops no EM voids develop and the resistance is stable. The microbump, which had lowest solder-to-Cu ratio, was measured to be immortal since its solder had totally transformed at time zero and subsequent EM testing did not alter it.

The electromigration behavior of copper pillars for different current directions and pillar shapes

A significant asymmetry in electromigration behavior was observed for copper pillars depending on the electron current direction; the electromigration performance is very robust for an electron source at the die-side, but vulnerable to the opposite electron flow direction. Through extensive failure analysis, it was observed that die-side electron source leads to a stable layering of intermetallic compounds and no electromigration-induced voiding, while the substrate-side electron source leads to more extensive transformation into intermetallic compounds at the expense of the copper trace as well as electromigration-induced voiding. These phenomena were exacerbated by narrower trace widths but improved by an oblong pillar shape. Further, the presence of a nickel cap between the solder and pillar did not significantly impact electromigration lifetime.

The impact of 45 to 28nm node-scaling on the electromigration of flip-chip bumps

The impact of 45nm to 28nm node-scaling on the electromigration of lead-free flip-chip bumps has been studied. Specifically, different UBM and PI open sizes as well as plated Ni and sputtered Cu UBM thicknesses were experimentally investigated. UBM sizes between 84 and 65 μm directly impact lifetime, while PI open diameters between 30 to 20 μm did not. A current-density exponent (n) value of 1 was measured when Joule heating is neglected, thereby suggesting a void-growth-limited mechanism. This value increases to 2 or greater when Joule heating is included, showing that Joule heating can strongly impact Imax extrapolations. Also, a thin plated Ni layer (1.5μm) and a thin sputtered Cu layer (2kÅ) independently led to significant early fails due to improper barrier coverage (rather than the thickness of the layer), which enhanced intermetallic transformation and therefore electromigration failure.