Richard F. Rizzolo

Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities

Voltage noise characterization is an essential aspect of optimizing the shipped voltage of high-end processor based systems. Voltage noise, i.e. Variations in the supply voltage due to transient fluctuations on current, can negatively affect the robustness of the design if it is not properly characterized. Modeling and estimation of voltage noise in a pre-silicon setting is typically inadequate because it is difficult to model the chip/system packaging and power distribution network (PDN) parameters very precisely. Therefore, a systematic, direct measurement-based characterization of voltage noise in a post-silicon setting is mandatory in validating the robustness of the design. In this paper, we present a direct measurement-based voltage noise characterization of a state-of-the-art mainframe class multicoreprocessor. We develop a systematic methodology to generate noise stress marks. We study the sensitivity of noise in relation to the different parameters involved in noise generation: (a) stimulus sequence frequency, (b) supply current delta, (c) number of noise events and, (d) degree of alignment or synchronization of events in a multi-core context. By sensing per-core noise in a multi-core chip, we characterize the noise propagation across the cores. This insight opens up new opportunities for noise mitigation via workload mappings and dynamic voltage guard banding.

S/390 G5 CMOS microprocessor diagnostics

This paper describes the strategies and techniques used to diagnose failures in the IBM 600-MHz S/390® G5 (Generation 5) CMOS microprocessor and the associated cache chips. The complexity, density, cycle time, and technology issues related to the hardware, coupled with time-to-market requirements, have necessitated a quick diagnostic turnaround time. Beginning with the first prototype of the G5 microprocessor chip, intense chip diagnostics and physical failure analysis (PFA) have successfully identified the root causes of many failures, including process, design, and random manufacturing defects. In this paper, three different diagnostic techniques are described that have enabled the G5 to achieve its objective. An example is presented for each technique to demonstrate its effectiveness.

IBM Enterprise System/900 Type 9121 Model 320 air-cooled processor technology

The basic component of the new IBM Enterprise System/9000™ Type 9121 Model 320 processor is an air-cooled thermal conduction module (TCM). The fabrication of this module required the integration of new bipolar chips, CMOS SRAM chips, and ECL and DCS logic circuitry in a TCM that could dissipate heat by means of air cooling. The method and details of this process of integration are described and discussed.

System performance management for the S/390 parallel enterprise server G5

System performance management is a broad category of techniques that cover all aspects of obtaining maximum performance or speed from a given design. Items such as sorting methodology, critical path improvements, semiconductor line optimization, power-supply optimization, clock tuning, and cooling are part of performance management. Logic or architecture improvements that have a major effect on design, such as increasing cache size, are usually not included.

Robust power management in the IBM z13

The power management strategy adopted for the IBM z13™ processor chip (referred to as the CP or Central Processor chip) is guided by three basic principles: (a) controlling the peak power consumption by setting a realistic limit on the so-called thermal design power or thermal design point (TDP) driven by customer workloads and maximum-power stress microbenchmarks; (b) reduction of the voltage margin by using a novel dynamic guard-banding technique; and (c) the creation of a rich new set of fine-grained, time-synchronized sensors that track performance, power, temperature, and power management behavior for a running machine. A prime requirement of the power management architecture is that the efficient control mechanisms be designed in such a manner that the high standards of IBM z Systems™ application performance and reliability be maintained without any compromise. In this paper, we describe the key features constituting the z13 CP robust power management architecture and design that meet the stipulated objectives.

Backside optical emission diagnostics for excess I/sub DDQ/

Backside optical emission was used to diagnose excess quiescent current in a multi-million gate microprocessor. Emission images showed the current was due to FETs improperly set in a conducting state. The utility of backside optical emission for IC diagnostics is discussed, and requirements for optical detectors and sample preparation are considered.

Design methods for attaining IBM System z9 processor cycle-time goals

Cycle-time targets were set for the IBM System z9TM processor subsystem prior to building the system, and achieving these targets was one of the biggest challenges we faced during hardware development. In particular, although the processor-subsystem cycle-time improvement was driven primarily by the technology migration from CMOS 9S (130-nm lithography) for the prior IBM System z990 to CMOS IOSO (90-nm lithography) for the new system, the cooling capability for the System z9 resulted from a direct migration of the System z990 implementation with very limited improvements. The higher device current leakage and power associated with the technology migration, combined with the fixed cooling capability, created a technology challenge in which the subsystem cycle time and performance were potentially limited by cooling capability. Our solution emphasized silicon technology development, chip design, and hardware characterization and tuning. Ultimately, the System z9 processor subsystem achieved operation at 1.7 GHz, which exceeded the original target.

26.2 Power supply noise in a 22nm z13™ microprocessor

Successful power supply noise mitigation requires a system-level approach that includes design and modeling of the mitigation circuits with the power delivery network (PDN) on the chip, the chip module, the backplane, and the voltage regulator module (VRM). Traditionally, periodic square-wave activity patterns with all cores in sync, which yield low-frequency (LF) or mid-frequency (MF) impedance peaks associated with the backplane and chip/module, respectively, are considered to give rise to the worst case power supply noise. However, voltage droops that are both deeper and faster at a single victim core are created when cores change activity in more complicated patterns, termed as perfect storms in this work. These patterns excite high-frequency (HF) modes that are not stimulated when all cores switch simultaneously, and require an accurate model of the packaged chip, including effective core-to-core inductances due to currents traveling between cores through low-resistance module planes.

High-Voltage and High-Power PLL Diagnostics using Advanced Cooling and Emission Images

In this paper, the paper discuss a diagnostics methodology based on the combined use of advanced chip cooling technology and high-resolution time-integrated images of the light emission due to off-state leakage current (LEOSLC). The methodology was successfully applied to the debug of an IBM microprocessor chip fabricated in the 90 nm SOI technology generation