Peilin Song

A novel scan chain diagnostics technique based on light emission from leakage current

Scan chain diagnostics have become more important than ever due to the increasing complexity of VLSI designs, as more and more scan latches/flip-flops are utilized in designs, especially in microprocessors. At the same time, the off-state leakage current of CMOS technology grows exponentially from one generation to the next one. This fact imposes a big challenge on the chip design, packaging, cooling, etc. However, innovative applications, based on the detection of light emission due to off-state leakage current (LEOSLC) have been developed for testing and diagnosing modern VLSI circuits. We show that LEOSLC can be used to effectively debug, diagnose, and localize defects in a broken scan chain.

Diagnosis and characterization of timing-related defects by time-dependent light emission

Technological advances such as flip-chip packaging, multiple hierarchical wiring planes, and ultra-high frequencies reduce the effectiveness of conventional diagnostic techniques. It has recently been demonstrated that light pulses emitted during circuit switching can be used to characterize the behaviour of integrated circuits. In this paper, a new method of circuit characterization using this technique is described. An example of the diagnosis of a timing failure caused by a resistive path to a single transistor is described.

Testing and diagnostics of CMOS circuits using light emission from off-state leakage current

In recent years, innovative applications based on the detection of emission sources such as the light emission from off-state leakage current (LEOSLC) of CMOS transistors have been developed for testing and diagnosing modern ultralarge-scale integration circuits. In this paper, we show that LEOSLC can be used to effectively debug circuits, localize defects with a quick turn around time, read the logic state of gates, and extract the internal voltage drop of power distribution grids among others.

Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs

An analytical model has been developed to provide physical design guidelines to suppress CDE-induced latchup in CMOS ICs. The design guidelines implemented in two test chips in IBMs 130nm technology successfully suppressed latchup against transient pulses of up to 6A peak current and against DC current pulses (EIA/JESD 78 test) of +/- 400mA.

Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip

This paper describes the test tool methodology used for the IBM S/390 microprocessor. An efficient, effective, and automated process providing correct-by-construction test pattern generation, an effective test pattern set, and diagnostics were required. This paper explains the techniques used to accomplish this along with explaining why the method was chosen and how it helped expedite the process.

On-chip Real-Time Power Supply Noise Detector

A new on-chip real-time noise detector that can be used for detecting voltage surges and droops on the internal power supply of VSLI circuits is presented. The noise detector is compact, and has the ability of detecting dc levels and high frequency on-chip transients of the power supply voltage. The detector has been implemented in a 90 nm CMOS technology, and has an area of 50times100 mum2. The measured results show that the detector can detect overshoots and undershoots of less than 1 ns, and as small as 20 mV

Transmission line pulse picosecond imaging circuit analysis methodology for evaluation of ESD and latchup

This paper will demonstrate the synthesis of the high current pulse source method (e.g. used in transmission line pulse (TLP) systems) and the Picosecond Imaging Circuit Analysis (PICA) tool for the evaluation. of electrostatic discharge (ESD) and latchup phenomenon. In this fashion, the evolution of ESD and latchup can be evaluated in semiconductor devices, and in peripheral circuits at a wafer level or product level. The methodology described in this publication allows for visualization of ESD and latchup, events (e.g. animation in a picosecond time regime). The synthesis of the transmission line pulse (TLP) method and the PICA method allows for the extension of the ESD TLP methodology to terminal currents and spatial and time domain analysis for electrical characterization and reliability analysis, and the high current pulsed source extends the utilization of the PICA methodology for failure analysis on wafer and chip levels.

Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor

We propose a novel ultralow-power, high-sensitivity, bias-free sub-threshold process variation sensor for monitoring the random variations in the threshold voltage. The proposed sensor characterizes the threshold voltage mismatch between closely spaced, supposedly identical transistors using the exponential current-voltage relationship of sub-threshold operation. The sensitivity of the proposed sensor is 2.3× better than the previous sensor reported in the literature which utilizes above-threshold operation. To further improve the sensitivity of the proposed sensor, an amplifier stage working in the sub-threshold region is designed. This enables 4× additional increase in sensitivity. A test-chip containing an array of 128 PMOS and 128 NMOS devices has been fabricated in 65-nm bulk CMOS process technology. A total of 28 dies across the wafer have been fully characterized and the random threshold voltage variations are reported here.

MARVEL — Malicious alteration recognition and verification by emission of light

This paper presents a new technique for detecting chip alterations using intrinsic light emission in combination with electrical test. The key idea of this method is based on the fact that any active device emits infrared light emission when it is powered on. High sensitivity photon detectors can be employed to capture the weak emission while the chip under test is powered on and electric stimuli are applied to it. In particular, two main families of electrical test modes, static and dynamic, can be applied. Positive results of the application of this methodology as well as key challenges will be discussed in the paper, including spatial resolution, imaging processing, data interpretation, etc.

Photon emission microscopy of inter/intra chip device performance variations

We propose a simple, noninvasive, optical technique to measure intra-wafer and intra-chip MOSFET performance variations. Technique utilizes correlation between device performance and weak near-infrared emission from its off-state current. It maps performance variations, producing quantitative data. We experimentally demonstrate our technique on 130 nm SOI microprocessor.