Richard Jordan

A 256-Mcell Phase-Change Memory Chip Operating at

A fully integrated 256-Mcell multi-level cell (MLC) phase-change memory (PCM) chip in 90-nm CMOS technology is presented. The on-chip circuitry supports fast MLC operation at 4 bit/cell. A programmable digital controller is used to optimize closed-loop gain and timing of the iterative MLC programming scheme and two power-efficient 8-bit DACs support current-controlled as well as voltage-controlled write pulses. The read-out consists of a low-power auto-range frontend followed by a 6-bit cyclic ADC that converts the nonlinear PCM resistance in a range between 10 kΩ and 10 MΩ . A verilog-A model derived from a full 3-D simulation of the PCM cell was developed to simulate the complete chip. The chip was used to demonstrate operation at 2 bit/cell and programming below 10 μs with Ge 2Sb 2Te 5 (GST) based PCM cells at a raw bit error rate of ~ 2 × 10- 4. Two main roadblocks for MLC PCM are drift and endurance. The accuracy of the analog frontend in combination with the programmable controller enables drift mitigation at the system level and the exploration of new materials for MLC operation at 3+ bit/cell.

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For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory (PCM) for M-type storage class memory applications . The write and read bandwidth is equal to 533MB/s, and the random read latency is 37.5ns, while the write latency is 11.25ns supporting a random write cycle of 176.7ns. In addition, a record high switching speed of 128ns with good resistance distribution is demonstrated with a super-fast Set material.