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Dive into the research topics where Richard Lindsay is active.

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Featured researches published by Richard Lindsay.


IEEE Transactions on Device and Materials Reliability | 2008

Gate-Induced-Drain-Leakage Current in 45-nm CMOS Technology

Xiaobin Yuan; Jae-Eun Park; Jing Wang; Enhai Zhao; David C. Ahlgren; Terence B. Hook; Jun Yuan; Victor Chan; Huiling Shang; Chu-Hsin Liang; Richard Lindsay; Sung-Joon Park; Hyotae Choo

Gate-induced-drain-leakage (GIDL) current in 45-nm state-of-the-art MOSFETs is characterized in detail. For the current technology node with a 1.2-V power-supply voltage, the GIDL current is found to increase in MOSFETs with higher channel-doping levels. In contrast to the classical GIDL current generated in the gate-to-drain overlap region, the observed GIDL current is generated by the tunneling of electrons through the reverse-biased channel-to-drain p-n junction. A band-to-band tunneling model is used to fit the measured GIDL currents under different channel-doping levels and bias conditions. Good agreement is obtained between the modeled results and experimental data. In addition, the dependence of the GIDL current on body bias, lateral electric field, channel width, and temperature is characterized and discussed.


IEEE Transactions on Semiconductor Manufacturing | 2007

Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance

Armin Tilke; Chris Stapelmann; Manfred Eller; Karl-Heinz Bach; Roland Hampp; Richard Lindsay; Richard A. Conti; William C. Wille; Rakesh Jaiswal; Maria Galiano; Alok Jain

In the present work, a high aspect ratio process (HARP) using a new O3/TEOS based sub atmospheric chemical vapor deposition process was implemented as STI gapfill in sub-65-nm CMOS. Good gapfill performance up to aspect ratios greater than 10:1 was demonstrated. Since the HARP process does not attack the STI liner as compared to HDP, a variety of different STI liners can be implemented. By comparing HARP with HDP, the geometry dependence of nand p-FET performance due to STI stress is discussed


international integrated reliability workshop | 2007

Characterization and analysis of gate-induced-drain-leakage current in 45 nm CMOS technology

Xiaobin Yuan; Jae-Eun Park; Jing Wang; Enhai Zhao; David C. Ahlgren; Terence B. Hook; Jun Yuan; Victor Chan; Huiling Shang; Chu-Hsin Liang; Richard Lindsay; Sung-Joon Park; Hyotae Choo

Gate-induced-drain-leakage (GIDL) current in 45 nm state-of-the-art MOSFETs is characterized in detail. For the current technology node with a 1.2 V power-supply voltage, the GIDL current is found to increase in MOSFETs with higher channel-doping levels. In contrast to the classical GIDL current generated in the gate-to-drain overlap region, the observed GIDL current is generated by the tunneling of electrons through the reverse-biased channel-to-drain p-n junction. A band-to-band tunneling model is used to fit the measured GIDL currents under different channel-doping levels and bias conditions. Good agreement is obtained between the modeled results and experimental data.


Archive | 2005

Semiconductor device with a buried gate and method of forming the same

Richard Lindsay; Matthias Hierlemann


Archive | 2011

Integrated Circuits and Methods of Design and Manufacture Thereof

Henning Haffner; Manfred Eller; Richard Lindsay


Archive | 2014

Silicided semiconductor structure and method of forming the same

Jiang Yan; Henning Haffner; Frank Huebinger; Sun-OO Kim; Richard Lindsay; Klaus Schruefer


Archive | 2010

Semiconductor Devices with Active Regions of Different Heights

Frank Huebinger; Richard Lindsay


Archive | 2012

Buried gate transistor

Richard Lindsay; Matthias Hierlemann


Archive | 2007

Method of implanting a non-dopant atom into a semiconductor device

Richard Lindsay; Yong Meng Lee; Manfred Eller


Archive | 2007

Structure and Method of Producing Isolation with Non-Dopant Implantation

Richard Lindsay; Yong Meng Lee; Manfred Eller

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