Manfred Eller

Anti-fuse memory array embedded in 14nm FinFET CMOS with novel selector-less bit-cell featuring self-rectifying characteristics

A novel anti-fuse memory array is presented in this paper featuring one-capacitor (1C) per bit-cell design and fully compatible with 14nm FinFET CMOS technology. The rectifying I-V characteristics of the metal-insulator-semiconductor (MIS) structure after programming prevents the sneak current in the cross-point array, therefore no need for select transistor in each cell. Thus enables the smallest reported bit-cell with area measuring 0.036 μm2.

Variation improvement for manufacturable FINFET technology

This works examines the sources of electrical variation for FinFET technology based on silicon data from 90nm contacted poly pitch, dual-epitaxy, and RMG (replacement metal gate) transistor. A simple statistical model is used to predict electrical variation based on physical variation that can be measured much earlier in the processing flow. The model is also used to define specification and control limits for physical variation to support the electrical variation specified in SPICE models. Gate stack, Junction, and Gate height variation are identified to be the key contributors to threshold voltage variation for FinFET technology. A case study is also presented on controlling gate height to the desired specification limits by improving across chip, within wafer, wafer to wafer, and lot to lot variation at multiple process steps.

Novel N/PFET Vt control by TiN plasma nitridation for aggressive gate scaling

A novel N/PFET threshold voltage (Vt) control scheme was developed for aggressive gate scaling. TiN plasma nitridation reduces absolute Vt by 100mV for both NFETs and PFETs at the same time without photolithography step increase and performance or reliability penalty. TiN plasma nitridation does not need additional work function metal (WFM) to control Vt and hence allows thicker gate contact metal for low gate resistance and improved AC performance.

Influence of stress induced CT local layout effect (LLE) on 14nm FinFET

In this paper, we present a new local layout effect in 14nm FinFET due to different CT layout designs (CT extension, CT spacing, and PC past RX distance). Based on 14nm FinFET experimental data, the CT LLE effect induces up to 50mV Vtsat shift, and ∼20% current change. NFET performance is enhanced by ∼7%, while the PFET performance shows slight degradation. Based on TCAD simulation, the CT LLE is fully analyzed and explained by the tensile stress induced in the inter-layer dielectric (ILD).

Modeling the impact of the vertical doping profile on FinFET SRAM V T mismatch

The basic multi-gate Vt variation model for uniform doping is extended to support a 2-region fin doping methodology that provides good agreement with Vt mismatch measurements as well as useful insights into how the non-uniform fin doping impacts the mismatch. The methodology displays good agreement for both NMOS and PMOS SRAM devices from a FinFET process. The NMOS Vt mismatch as a function of Vt is found to follow the non-uniform doping model while the PMOS Vt mismatch is higher due to both high, non-uniform doping as well as P-metal gate workfunction induced mismatch.

Advanced RMG module to improve AC/DC performance for 14nm FinFETs and beyond

An advanced Replacement Metal Gate (RMG) module was developed for 14nm node FinFETs and beyond. STI oxide extra recess increases on-current without any dedicated Source and Drain (SD) optimization. Tungsten (W) selective etch recesses work function metal (WFM), which reduces gate-contact capacitance, and improves AC performance and yields by increasing gate-contact space. Combination of work function (WF) adjust treatment and WFM optimization was applied to achieve wide range of threshold voltage (Vt) control for multiple Vt (multi-Vt) devices without any performance penalty.