Richard W. Foote

Impact of buried layer processing on gate oxide integrity [CMOS processing]

Buried layers are used in bipolar devices to lower collector resistance in bulk silicon and SOI (silicon-on-insulator) technologies. They are also used with deep trench for isolating different devices types. This work investigates the effect of buried layer processing on CMOS capacitor reliability, comparing results between bulk silicon and SOI substrates. Opposing results from bulk and SOI technologies indicate different degradation mechanisms at play. The SOI starting material requires that metal contaminant gettering be taken in to account in the processing of the buried layers.

Physical modeling and alleviation of shallow-trench-isolation charging effects in silicon-on-insulator complementary bipolar technology

Oxide charging, adversely influencing PNP collector-base capacitance, has been observed and modeled physically in a complementary bipolar process that uses dielectric isolation. A practical solution to alleviate this effect is described along with trade-offs involved in process and device design.