Richard Wong

SRAM Interleaving Distance Selection With a Soft Error Failure Model

The significance of multiple cell upsets (MCUs) is revealed by sharing the soft-error test results in three major technologies, 90 nm, 65 nm, and 45 nm. The effectiveness of single-bit error correction (SEC) codes can be maximized in mitigating MCU errors when used together with the interleaving structure in memory designs. The model proposed in this paper provides failure probability to probabilistically demonstrate the benefits of various interleaving scheme selections for the memories with SEC. Grouped events such as MCU are taken into account in the proposed model by using the compound Poisson process. As a result of the proposed model, designers can perform predictive analysis of their design choices of interleaving schemes. The model successfully showed the difference in failure probability for different choices of interleaving schemes. The model behaved as the upper bound for failure probability when compared to the neutron test data with the 45-nm static-random-access memory (SRAM) design.

Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals

Ternary content addressable memory (TCAM) is more susceptible to soft errors than static random access memory (SRAM). The large di/dt issue during comparison operation reduces operating voltage ranges, which in turn reduces soft error immunity. The tight structural coupling of TCAM comparison circuits and memory cells does not allow for an interleaving design scheme in mitigating soft errors. Regular scrubbing of stored content can greatly mitigate the reliability issue caused by soft errors. However, frequent scrubbing can also affect device performance. The scrubbing interval should be determined to facilitate both reliability and performance. This paper proposes a novel, model-based approach that includes both single-bit upsets (SBUs) and multi-cell upsets (MCUs) to determine the scrubbing interval by predictive and probabilistic failure rate analysis. This model uses the compound Poisson (CP) process to count clustered random events, which are common phenomena of soft errors in technologies that use chips under 90 nm. The 20 M TCAM with 90-nm CMOS technology was tested with 180-MeV neutron strikes. The scrubbing interval determined based on the proposed model is applied to the TCAM test results. The failure probabilities based on the CP model showed 31% overestimation on average compared to the same from the test data. Such overestimation is mainly due to the independent upset assumption in the proposed model and can enable use of the model as worst case analysis. The worst case comparison with the test data showed 1.7% overestimation, which can tell the proposed model is effective in predicting upper-bound soft error reliability.

Effects of scaling on muon-induced soft errors

Experimental results are presented that indicate technology scaling increases the sensitivity of microelectronics to soft errors from low-energy muons. Results are presented for 65, 55, 45, and 40 nm bulk CMOS SRAM test arrays. Simulations suggest an increasing role of muons in the soft error rate for smaller technologies.

Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS

In modern CMOS processes, soft errors and metastability are two prominent failure mechanisms. Radiation induced single event upsets, or soft-errors, have become a dominant failure mechanism in sub-100 nm CMOS memory and logic circuits. The effects of metastability have also becoming increasingly significant in high-speed applications implemented in nanometric processes. In this paper the design trade-offs for flip-flops between performance, soft-error robustness and metastability are described. Soft-error robust flip-flops are implemented based on both the DICE cell and the Quatro cell. SPICE simulations are used to characterize the transient performance and metastability robustness, and device level simulations were performed to quantify the soft-error robustness. The flip-flops were fabricated in the TSMC 40 nm process and radiation measurements were performed at several test facilities. The Quatro flip-flop showed improved soft-error robustness and metastability when compared with a reference D flip-flop and a DICE flip-flop.

Protection of Memories Suffering MCUs Through the Selection of the Optimal Interleaving Distance

Interleaving, together with single error correction codes (SEC), are common techniques to protect memories against multiple cell upsets (MCUs). This kind of errors is increasingly important as technology scales, becoming a prominent effect, and therefore greatly affecting the reliability of memories. Ideally, the interleaving distance (ID) should be chosen as the maximum expected MCU size. In this way, all errors in an MCU would occur in different logical words, thus being correctable by the SEC codes. However, the use of large interleaving distances usually results in an area increase and a more complex design of memories. In this paper, the selection of the optimal interleaving distance is explored, keeping the area overhead and complexity as low as possible, without compromising memory reliability.

Thermal neutron soft error rate for SRAMS in the 90NM–45NM technology range

The thermal neutron soft error rate (SER) was measured systematically on SRAM cells in the technology range of 90nm to 45nm. We report here a substantial SER sensitivity with neutron energies below 0.4eV for many SRAM cells.

Design and Analysis of Low-Voltage Low-Parasitic ESD Protection for RF ICs in CMOS

This paper reports design, analysis and optimization of a new low-parasitic, very-low-triggering-voltage dual-directional silicon-controlled rectifier (VLTdSCR) type electrostatic discharge (ESD) protection structure and its cross-coupling ultra-low-triggering ESD protection circuitry (CULTdSCR) implemented in a commercial 0.18 μm CMOS. Mixed-mode ESD simulation-design technique is used to verify the new embedded punch-through and gate cross-coupling ESD trigger-assisting techniques devised to achieve ultra-low ESD triggering for SCR-type ESD protection in CMOS. Experiment shows a record low ESD triggering voltage (Vt1) of 3.83 V, noise figure (NF) of 0.2 dB, parasitic ESD capacitance (CESD) of 150 fF and prompt response to very fast ESD pulses with rising time (tr) down to 100 pS. The new ESD design achieves a very high dual-directional charged device model (CDM) ESD protection capability of ~7 V/μ m2.

Multicenter comparison of alpha particle measurements and methods typical of semiconductor processing

Alpha counting measurement methods have been widely used in the semiconductor industry for many years to assess the suitability of materials for semiconductor production and packaging applications. Although a number of published articles describe aspects of this counting, a multicenter, comparative trial has not been carried out to assess the methodological accuracy of current methods. This paper reports on experience with a 9 center, international, round-robin style trial using a shared set of samples to quantify variability in alpha emission measurements. Four samples representing low and ultralow alpha materials were counted by each participating lab in a blinded trial. The consensus mean emissivity for low alpha material was estimated as 30.9 khr-1-cm-2 with a range from 20.2 to 45.5, less than half of which can be attributed to counting uncertainty or other known sources of error. A strong correlation for replicate measurements within a lab was also observed supporting the conclusion that there are systematic variations in equipment or calibration among labs. Eleven of 23 measurements of ultralow alpha materials were within 1 standard deviation of the consensus mean and 7 were at or below background. The high level of counting uncertainty for these measurements is thought to be sufficient to mask any systematic variation similar to the low alpha observations. Comparison of the reported values with a standard calculation demonstrates that there are also differences in the interpretation of the values reported for emissivity and error, underscoring the need for careful interpretation of results.

Variation of SRAM Alpha-Induced Soft Error Rate with Technology Node

This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.

Supply Voltage Dependence of Heavy Ion Induced SEEs on 65 nm CMOS Bulk SRAMs

Soft Error Rates (SER) of hardened and unhardened SRAM cells need to be experimentally characterized to determine their appropriate applications in radiation environments. This characterization is especially important when low supply voltage is preferred. In this paper, we developed an SRAM test chip with four cell arrays including two types of unhardened cells (standard 6T and subthreshold 10T) and two types of hardened cells (Quatro and DICE). This test chip was fabricated in a 65 nm bulk technology and irradiated by heavy ions at different supply voltages. Experimental results show that the SERs of 6T and 10T cells present significant sensitivities to supply voltages when the particle linear energy transfers (LETs) are relatively low. For Quatro and DICE cells, one does not consistently show superior hardening performance over the other. It is also noted that Quatro cells show significant advantage in single event resilience over 10T cells although they consume similar areas. TCAD simulations were carried out to validate the experimental data. In addition, the error amount distributions follow a Poisson distribution very well for each type of cell array.