Rita Fung

An SEU-Tolerant DICE Latch Design With Feedback Transistors

This paper presents an SEU-tolerant Dual Interlocked Storage Cell (DICE) latch design with both PMOS and NMOS transistors in the feedback paths. The feedback transistors improve the SEU tolerance by increasing the feedback loop delay during the hold mode. The latch design was implemented in a shift register fashion at a 130-nm bulk CMOS process node. Exposures to heavy-ions exhibited a significantly higher upset LET threshold and lower cross-section compared with the traditional DICE latch design. Performance penalties in terms of write delay, power, and area are non-significant compared to traditional DICE design.

Supply Voltage Dependence of Heavy Ion Induced SEEs on 65 nm CMOS Bulk SRAMs

Soft Error Rates (SER) of hardened and unhardened SRAM cells need to be experimentally characterized to determine their appropriate applications in radiation environments. This characterization is especially important when low supply voltage is preferred. In this paper, we developed an SRAM test chip with four cell arrays including two types of unhardened cells (standard 6T and subthreshold 10T) and two types of hardened cells (Quatro and DICE). This test chip was fabricated in a 65 nm bulk technology and irradiated by heavy ions at different supply voltages. Experimental results show that the SERs of 6T and 10T cells present significant sensitivities to supply voltages when the particle linear energy transfers (LETs) are relatively low. For Quatro and DICE cells, one does not consistently show superior hardening performance over the other. It is also noted that Quatro cells show significant advantage in single event resilience over 10T cells although they consume similar areas. TCAD simulations were carried out to validate the experimental data. In addition, the error amount distributions follow a Poisson distribution very well for each type of cell array.

Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology

Two types of clock networks including clock mesh and a buffered clock tree in a daisy-chain style were utilized to synchronize 5 DFF chains and fabricated in a 28 nm bulk CMOS technology. Alpha and proton particles did not trigger any errors indicating the significant single event tolerance of these clock networks. Heavy ion results for the data input pattern of checkerboard (alternate 1 and 0) are presented showing few occurrences of burst errors induced by single event transients (SETs) in the buffered clock tree at relatively high LET values. The same phenomena were observed in laser tests. Clock mesh is therefore proven to be less sensitive to SETs, if pre-mesh drivers do not generate transients. Otherwise, clock mesh possesses lower tolerance, as demonstrated in previous work. Moreover, these burst errors occurred (1) simultaneously in a DFF chain and its subsequent chains, or (2) in a single chain with subsequent chains unaffected. The distinct mechanisms of these burst errors were found to be the electrical masking effect of the daisy-chain clock buffers.

Networking industry trends in ESD protection for high speed IOs

Data rates in networking applications have increased as demand for more data increases. To achieve the high performance, the data rates in high speed IOs have continued to increase. These high data rates require the IO capacitances have to be very low. ESD protection structures have traditionally been large to handle the large transient currents. Recently, the high speed IO has limited the capacitance associated with ESD structures, making ESD protection design for high speed IOs extremely challenging. This paper will discuss the networking industrys trends in high speed IOs, the capacitance requirements and resulting challenges for ESD protection designs. To achieve the proper ESD protection, on chip ESD protection schemes will need to change and/or ESD protection specifications may need to lower targeted protection levels. This is a hotly argued topic in the high speed networking industry, which may change the next-generation ESD protection design dramatically. We will discuss the possible ESD design outcomes due to the high speed IOs scaling trends.

An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology

In this paper, we present D flip-flop, Quatro, and stacked Quarto flip-flop designs fabricated in a commercial 28-nm CMOS FDSOI technology. Stacked-transistor structures are introduced in the stacked Quatro design to protect the sensitive devices of the original structure. Striking either of the stacked devices will not upset the latch because the conduction path to the supply rail is still cut off by the other off-state device. The irradiation experimental results substantiate that the stacked Quatro design has significantly better SEU tolerance (e.g., higher heavy ion upset Linear Energy Transfer threshold and smaller cross-section data) than the reference designs. It introduces power and area penalties because the proposed design duplicates and stacks two sensitive PMOS devices. Additionally, the impact of technology scaling on Quatro in various technology nodes (130-nm, 65-nm, and 40-nm) has been studied suggesting decreasing upset threshold and decreasing cross-section data.

Analysis of advanced circuits for SET measurement

Single Event Transients (SETs) are a growing concern in advanced integrated circuits yet techniques to accurately characterize the cross-section and pulse width of SETs are less mature than those for measuring SEUs. We present four circuits for measuring SETs, an analysis of their capabilities and the subtleties in their implementation. Post-layout circuit simulation results are presented for a test-chip implemented in 28 nm FSDOI technology and integrating these detectors.

Charged device ESD threats with high speed RF interfaces

High speed RF interfaces operating in tens Gbit/s range have limited ESD immunity. These interfaces are accessible when electro-mechanics are assembled on a printed circuit board. Charged device ESD threats due to charged assemblies with less than 1 pF source capacitances are discussed in this paper.

Evaluation of SEU Performance of 28-nm FDSOI Flip-Flop Designs

In this paper, a variety of flip-flop (FF) designs fabricated in a commercial 28-nm Fully-Depleted Silicon on Insulator (FDSOI) technology are evaluated for their single-event upset performance with ions and pulsed laser experiments. These FF designs consist of unhardened DFF, hardened DFF with stacked transistors in the inverters, and the layout-optimized DFFs. These DFFs were exposed to alpha particles and heavy ions (HIs). None of the hardened DFFs exhibit any errors up to a Linear Energy Transfer (LET) of 50 MeV*cm2/mg under normal irradiation, and a layout-based hardened DFF started to see errors at a LET of 50 MeV*cm2/mg with the tilt angle of 600. The testing data substantiates effective SEU reduction of these hardened designs. Two-photon absorption (TPA) laser experiments were carried to test these DFF designs, and the results showed that pulsed laser may not be a valid tool to evaluate the FFs designed with nano-scale SOI stacked structures. This brings new challenges in laser hardness assurance for RHBD designs.

An ESD case study with high-speed interface in electronics manufacturing and its future challenge

A networking semiconductor component with 25 Gbps high-speed interface experienced high manufacturing failure rate with CDM-like failure signature at contract manufacturer; design of experiment was performed and ESD source was located. Problem details, solution, future challenge and industry awareness are discussed in this paper.

A Circuit-Based Approach for Characterizing High Frequency Electromigration Effects

A test chip for studying electromigration (EM) effects under various dc and ac stress conditions was implemented in a 32-nm-high-k metal gate process. The stress current, which can be either dc, pulsed dc, square ac, or real ac, was generated on-chip and applied to 60 devices under test (DUTs) in parallel. An on-chip voltage-controlled oscillator was designed to generate a stress frequency higher 1 GHz while on-chip metal gate heaters were used to raise the DUT temperature to >300 °C for accelerated testing. Both abrupt and progressive failures were observed under dc and pulsed dc stress modes. The abrupt failures could be further divided into two categories based on the final resistance value. Although no ac stress induced failures were observed during our extensive stress experiments, ac stress did have an impact on the subsequent dc EM lifetime. Two possible scenarios are given to explain the high frequency EM results.