Rinkle Jain

A 0.45–1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS

A fully integrated switched capacitor voltage regulator (SCVR) with on-die high density MIM capacitor, distributed across a 14 KB register file (RF) load is demonstrated in 22 nm tri-gate CMOS. The multi-conversion-ratio SCVR provides a wide output voltage range of 0.45-1 V from a fixed input voltage of 1.225 V. It achieves 63-84% conversion efficiency and supports a maximum load current density of 0.88 A/mm2. The area overhead of the dedicated SCVR on the load is 3.6%. Measured data is presented on various performance indices in detail. Subsequent learning on tradeoffs between various factors like capacitance characteristics, conversion efficiency and current density are delineated and, correlated with theoretical estimates. Performance of RF array shows comparable results when powered with the SCVR and the external rail. The all-digital, modular design allows efficient spatial distribution across the load and hence robust power delivery. The extremely fast response times in the order of few nanoseconds is targeted to benefit agile power management. This work evinces voltage regulator technology as a standard homogenous CMOS component, which can proliferate DVFS domains for maximum energy and area benefits.

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep

In this paper, we present a low-power graphics processing core that achieves a 40% improvement in peak energy efficiency using dual-VCC arrays, adaptive clocking for voltage droop mitigation, and state retention capability with an integrated retention clamping circuit for low-power sleep mode. The 22nm testchip includes a graphics execution core connected to an SRAM array and test controller used for storage and delivery of at-speed test vectors. Correct execution of the tests is validated through a multiple-input signature register (MISR), which accumulates key signals in the core and generates a 32b signature at test completion.

8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation

A graphics execution core in 22nm improves energy efficiency across a wide DVFS range, from the near-threshold voltage (NTV) region, where circuit assist lowers intrinsic VM!N, to the turbo region, where adaptive clocking reduces the voltage-droop guard-band [1]. When powered with a shared rail, however, energy is wasted in the core if other blocks demand higher voltage and performance. Alternately, a per-core fully-integrated voltage regulator (VR) provides a cost-effective means to realize autonomous DVFS [2-4]. In this paper, we present a graphics core that is supplied by a fully integrated and digitally controlled hybrid low-drop-out (LDO)/switched-capacitor voltage regulator (SCVR) with fast droop response (Fig. 8.6.1). While the LDO VR enables high power density and is area efficient, as it can use existing power headers originally employed for bypass/sleep modes, it suffers from efficiency loss at low VOUT. An SCVR, on the other hand, has improved conversion efficiency across a wide VOUT range. In an area-constrained design, however, the limited size of the SCVRs fly capacitors and associated configurable power stages sets an upper bound on the SCVRs maximum power density, restricting its use to lower VOUT. This LDO/SCVR combination delivers the power required by the core at a high VOUT of 0.92V with 84% LDO efficiency, while extending to a low VOUT of 0.38V with 52% SCVR efficiency from a 1.05V VIN. Compared to a shared-rail scheme, the hybrid VR enables 26% to 82% reduction in core energy versus 26% to 67% if solely the LDO is used.

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator

A digitally-controlled fully integrated voltage regulator (IVR) enables wide autonomous DVFS in a 22 nm graphics execution core. Part of the original power header is converted into a hybrid power stage to support digital low-dropout (DLDO), and switched-capacitor voltage regulator (SCVR) modes, in addition to the original bypass and sleep modes. Using voltage sensing, tunable replica circuit, or a core warning signal, the IVR detects and quickly responds to fast voltage droops to support fast dynamic workload changes without performance degradation. In a prototype, a 3D graphics execution core is powered up by the proposed hybrid IVR demonstrating measured 26% and 82% reduction in core energy in the turbo and the near-threshold voltage (NTV) modes, respectively. The total area overhead of the proposed hybrid IVR is 4% of the core compared to 2% from the original power header. Our digitally assisted control for the droop response shows ~ 75% core frequency improvement at 0.84 V.

A novel control technique to eliminate output-voltage-ripple in switched-capacitor DC-DC converters

A novel ripple mitigation technique is proposed for switched-capacitor voltage regulators (SCVR), which eliminates the output voltage ripple without using multi-phase interleaving. An inner control loop matches the SCVRs switch current to the load current on a cycle by cycle basis. A 2-phase 3∶2 SCVR is designed in 45-nm CMOS process with the proposed control. For a 1.8 V to 1.05 V /40 mA converter, the proposed mitigation loop reduces the peak-to-peak output ripple from 330 mVp-p to 17 mVp-p, using total output capacitance of 4 nF/A. In addition, the proposed technique yields excellent regulation transient response.

A novel Switched Capacitor circuit for efficient voltage regulation

Switched capacitor (SC) circuits are used as voltage regulators in very low power applications. They are not suitable to generate regulated output voltage for medium or high power applications especially with a wide range of input voltages. A novel fixed type SC circuit is presented that addresses this issue and provides regulated voltage at high efficiency over a wide range of input voltage. This paper presents how charge flow analysis can be extended to this converter, which simplifies analysis considerably. Analysis, simulation results and experimental results from prototype fabricated on a PCB are presented.

Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS

Active conduction modulation techniques are demonstrated in a fully integrated multi-ratio switched-capacitor voltage regulator with hysteretic control, implemented in 22nm tri-gate CMOS with high-density MIM capacitor. We present (i) an adaptive switching frequency and switch-size scaling scheme for maximum efficiency tracking across a wide range voltages and currents, governed by a frequency-based control law that is experimentally validated across multiple dies and temperatures, and (ii) a simple active ripple mitigation technique to modulate gate drive of select MOSFET switches effectively in all conversion modes. Efficiency boosts upto 15% at light loads are measured under light load conditions. Load-independent output ripple of <;50mV is achieved, enabling fewer interleaving. Testchip implementations and measurements demonstrate ease of integration in SoC designs, power efficiency benefits and EMI/RFI improvements.

Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS.

Switch conductance modulation techniques are demonstrated in a fully integrated multi-ratio switched-capacitor voltage regulator with hysteretic control, in 22 nm tri-gate CMOS with high-density MIM capacitor. We present (i) an adaptive switch-size scaling scheme for maximum efficiency tracking across a wide range of voltages and currents, governed by a frequency-based control law that is experimentally validated across multiple dies and temperatures and, (ii) a simple active ripple mitigation technique that modulates the gate drive of select MOSFET switches effectively in all conversion modes. Efficiency improvements up to 15% are measured under low output voltage and load conditions. Load-independent output ripple of <;50 mV is achieved, enabling reduced interleaving. Test chip implementations and measurements demonstrate ease of integration in SoC designs, power efficiency benefits and EMI/RFI improvements.

A staircase conductance modulation scheme for input-current-shaping in switched-capacitor DC-DC converters

We present a digital feedback control scheme that mitigates input current discontinuity in Switched Capacitor Voltage Regulators. The switch resistance profile that results in constant input current is derived and implemented on a four-ratio regulator. The details of this digital scheme is presented. Simulations on 32nm CMOS show reduction of up to 70% in the input current peak.

Parallel feedback compensation for LDO voltage regulators

A novel low dropout (LDO) voltage regulator compensation technique is demonstrated. A parallel feedback path is used to insert a zero at approximately three times the output pole. The parallel feedback consists of passive elements only and occupies small area. The proposed technique completely eliminates the output pole at different load conditions and results in high LDO bandwidth, which achieves fast output tracking of the input reference and fast recovery of sudden load changes. Moreover, the output pole elimination at different load conditions enables the potential scaling of the error amplifier quiescent current with the load without compromising stability. The proposed LDO has been implemented in 65-nm TSMC low-power CMOS process, and achieves 0.24-ns response time at 94% current efficiency. For a 1.2-V input voltage and 1-V output voltage the regulator enables 79mVp-p output droop for a maximum load step.