S.-J. Wen

Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node

Neutron- and proton-induced single-event upset cross sections of D- and DICE-Flip/Flops are analyzed for designs implemented in a 40 nm bulk technology node. Neutron and proton testing of the flip/flops show only a 30%-50% difference between D- and DICE-Flip/Flop error rates and cross sections. Simulations are used to show that charge sharing is the primary cause for the similar failures-in-time (FIT) rates. Such small improvement in the single-event performance of the DICE implementation over standard D-Flip/Flop designs may warrant careful consideration for the use of DICE designs in 40 nm bulk technologies and beyond.

Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process

It has been predicted that upsets due to Single-Event Transients (SETs) in logic circuits will increase significantly with higher operating frequency and technology scaling. For synchronous circuits manufactured at advanced technology nodes, errors due to single-event transients are expected to exceed those due to latch upsets. Experimental results presented in this paper quantify the contribution of logic errors to the total Soft-Error Rate (SER) for test circuits fabricated in a 40 nm bulk CMOS technology. These results can be used to develop guidelines to assist circuit designers adopt effective hardening strategies to reduce the SER, while meeting performance specifications for high speed logic circuits.

Single-Event Performance and Layout Optimization of Flip-Flops in a 28-nm Bulk Technology

Alpha, neutron, and heavy-ion single-event measurements were performed on both high-performance and hardened flip-flop designs in a 28-nm bulk CMOS technology. The experimental results agree very well with simulation predictions and confirm that event error rates can be reduced dramatically using effective layout design.

Frequency Dependence of Alpha-Particle Induced Soft Error Rates of Flip-Flops in 40-nm CMOS Technology

In this paper, the alpha-particle induced soft error rate of two flip-flops are investigated as a function of operating frequency between 80 MHz and 1.2 GHz. The two flip-flops-an unhardened D flip-flop and a hardened pseudo-DICE flip-flop were designed in a TSMC 40 nm bulk CMOS technology. The error rates of both flip-flops increase with frequency. Analyses show that an internal single-event transient based upset mechanism is responsible for the frequency dependence of the error rates.

Single-Event Tolerant Flip-Flop Design in 40-nm Bulk CMOS Technology

In this paper, the radiation response of a single-event tolerant flip-flop design named the Quatro flip-flop is presented. Circuit level simulations on the flip-flop design show 1) the critical charge of the sensitive nodes to be greater than that of DICE flip-flop, 2) the number of sensitive nodes and the sensitive area to be fewer than that of DICE flip-flop. A test-chip designed and fabricated at the 40-nm bulk CMOS technology node consisting of Quatro, DICE, and standard D- flip-flops was used for heavy-ions, neutrons, and alpha particles exposures. The experimental results demonstrate superior performance of the Quatro flip-flop design over conventional DICE and D-flip-flop designs.

Technology Scaling Comparison of Flip-Flop Heavy-Ion Single-Event Upset Cross Sections

Heavy-ion experimental results from flip-flops in 180-nm to 28-nm bulk technologies are used to quantify single-event upset trends. The results show that as technologies scale, D flip-flop single-event upset cross sections decrease while redundant storage node flip-flops cross sections may stay the same or increase depending on the layout spacing of storage nodes. As technology feature sizes become smaller, D flip-flop single-event upset cross sections approach redundant storage node hardened flip-flops cross sections for particles with high linear energy transfer values. Experimental results show that redundant storage node designs provide > 100X improvement in single-event upset cross section over DFF for ion linear energy transfer values below 10 MeV-cm2/mg down to 28-nm feature sizes.

Impact of Supply Voltage and Frequency on the Soft Error Rate of Logic Circuits

Alpha particle irradiations of 28-nm combinational logic and flip-flop circuits under different supply voltage and frequency operating conditions are investigated. Results indicate that while the supply voltage has a strong impact on the alpha particle soft error rate of flip-flops, the combinational logic error rate is relatively unaffected by supply voltage variation. Simulations are used to explain the results and highlight the differences between low-LET alpha particle irradiation and heavy-ion irradiation as far as voltage dependence of the logic soft error rate is concerned. Moreover, frequency has a much stronger impact on the logic soft error rate as compared to the flip-flop soft error rate. As a result, the frequency at which soft errors from combinational logic circuits will exceed errors from flip-flops decreases as the voltage increases. The impact of these observations is discussed in the context of soft-error mitigation strategies.

The Contribution of Low-Energy Protons to the Total On-Orbit SEU Rate

Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. Grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.

Impact of technology scaling on the combinational logic soft error rate

Experimental results from alpha particle irradiation of 40-nm, 28-nm and 20-nm bulk technology circuits operating in the GHz range suggest that the combinational logic soft error rate (SER) per logic gate decreases with scaling. This rate of decrease for the logic SER with scaling, however, is not as high as that of the latch SER. As a result, the proportion of combinational logic soft errors at the chip level is shown to increase. Results suggest that alpha-particle logic SER of average sized circuits is about 20% of the latch SER at 20-nm node while it is only 10% at 40-nm at 500 MHz. Moreover, the frequency at which combinational logic SER exceeds latch SER decreases with scaling. Factors that influence logic soft error scaling trends, such as sensitive area, transient pulse-widths and latch characteristics, are estimated through simulations and soft-error rate predictions for future technology nodes are made.

Estimation of hardened flip-flop neutron soft error rates using SRAM multiple-cell upset data in bulk CMOS

Experimental neutron single-event error rates of 28-and 40-nm bulk CMOS hardened flip-flops are compared to various hardened flip-flop designs in literature. Using published 45-nm SRAM multiple-cell upset data, it is shown that the error rate of hardened flip-flop designs can be estimated by using the minimum sensitive node spacing from the flip-flop layout. Experimental data show that regardless of circuit topology of a hardened flip-flop, the redundant storage node spacing dominates neutron soft-error rates.