Rawad N. Al-Haddad

Layered Approach to Intrinsic Evolvable Hardware using Direct Bitstream Manipulation of Virtex II Pro Devices

An integrated platform for fast genetic operators is presented to support intrinsic evolution on Xilinx Virtex II pro field programmable gate arrays (FPGAs). Dynamic bitstream compilation is achieved by directly manipulating the bitstream using a layered design. Experimental results on a case study have shown that a full design as well as a full repair is achievable using this platform with an average time of 0.4 microseconds to perform the genetic mutation, 0.7 microseconds to perform the genetic crossover, and 5.6 milliseconds for one input pattern intrinsic evaluation. This represents a performance advantage of three orders of magnitude over JBITS and more than seven orders of magnitude over the Xilinx design tool driven flow for realizing intrinsic genetic operators on a Virtex II Pro device.

Adaptive Mitigation of Radiation-Induced Errors and TDDB in Reconfigurable Logic Fabrics

Self-reliance capabilities of mission-critical systems gain importance as technology scaling and logic capacity of SRAM-based reconfigurable devices increase. The Sustainable Modular Adaptive Redundancy Technique (SMART) is evaluated to optimize the reliability, availability, and energy efficiency of reconfigurable logic devices with a given area footprint. A Monte Carlo driven Continuous Markov Time Chain (CMTC) simulation is conducted to assess availability using runtime adaptation with SMART in comparison to conventional design-time static Triple Modular Redundancy (TMR) techniques. In harsh environments, adaptive redundancy is shown to improve system availability under lengthy repair times, and to a more significant degree under rapid recovery times. When compared to TMR, adaptive redundancy achieves power savings ranging from 22% to 29%, at a reduced area cost ranging from 17% to 24%, while maintaining comparable levels of availability.

Sustainability assurance modeling for SRAM-based FPGA evolutionary self-repair

A quantitative stochastic design technique is developed for evolvable hardware systems with self-repairing, replaceable, or amorphous spare components. The model develops a metric of sustainability which is defined in terms of residual functionality achieved from pools of amorphous spares of dynamically configurable logic elements, after repeated failure and recovery cycles. At design-time the quantity of additional resources needed to meet mission availability and lifetime requirements given the fault-susceptibility and recovery capabilities are assured within specified constraints. By applying this model to MCNC benchmark circuits mapped onto Xilinx Virtex-4 Field Programmable Gate Array (FPGA) with reconfigurable logic resources, we depict the effect of fault rates for aging-induced degradation under Time Dependent Dielectric Breakdown (TDDB) and interconnect failure under Electromigration (EM). The model considers a population-based genetic algorithm to refurbish hardware resources which realize repair policy parameters and decaying reparability as a complete case-study using published component failure rates.