Robert A. Groves

Frequency-independent equivalent-circuit model for on-chip spiral inductors

A wide-band physical and scalable 2-/spl Pi/ equivalent circuit model for on-chip spiral inductors is developed. Based on physical derivation and circuit theory, closed-form formulas are generated to calculate the RLC circuit elements directly from the inductor layout. The 2-/spl Pi/ model accurately captures R(f) and L(f) characteristics beyond the self-resonant frequency. Using frequency-independent RLC elements, this new model is fully compatible with both ac and transient analysis. Verification with measurement data from a SiGe process demonstrates accurate performance prediction and excellent scalability for a wide range of inductor configurations.

Current status and future trends of SiGe BiCMOS technology

The silicon germanium (SiGe) heterojunction bipolar transistor (HBT) marketplace covers a wide range of products and product requirements, particularly when combined with CMOS in a BiCMOS technology. A new base integration approach is presented which decouples the structural and thermal features of the HBT from the CMOS. The trend is to use this approach for future SiGe technologies for easier migration to advanced CMOS technology generations. Lateral and vertical scaling are used to achieve smaller and faster SiGe HBT devices with greatly increased current densities. Improving both the f/sub T/ and f/sub MAX/ will be a significant challenge as the collector and base dopant concentrations are increased. The increasing current densities of the SiGe HBT will put more emphasis on interconnects as a key factor in limiting transistor layout. Capacitors and inductors are two very important passives that must improve with each generation. The trend toward increasing capacitance in polysilicon-insulator-silicon (MOSCAP), polysilicon-insulator-polysilicon (Poly-Poly), and metal-insulator-metal (MIM) capacitors is discussed. The trend in VLSI interconnections toward thinner interlevel dielectrics and metallization layers is counter to the requirements of high Q inductors, potentially requiring a custom last metallization layer.

Foundation of rf CMOS and SiGe BiCMOS technologies

This paper provides a detailed description of the IBM SiGe BiCMOS and rf CMOS technologies. The technologies provide high-performance SiGe heterojunction bipolar transistors (HBTs) combined with advanced CMOS technology and a variety of passive devices critical for realizing an integrated mixed-signal system-on-a-chip (SoC). The paper reviews the process development and integration methodology, presents the device characteristics, and shows how the development and device selection were geared toward usage in mixed-signal IC development.

Frequency-independent equivalent circuit model for on-chip spiral inductors

A wide-band, physical and scalable 2-/spl Pi/ equivalent circuit model for on-chip spiral inductors is developed. Using frequency-independent RLC elements, it accurately captures R(f) and L(f) characteristics beyond the self-resonant frequency. This new model is fully compatible with both AC and transient analysis. Verification with measurement data demonstrates excellent scalability for a wide range of inductor configurations.

RF potential of a 0.18-/spl mu/m CMOS logic device technology

The radio-frequency (RF) performance of a 0.18-/spl mu/m CMOS logic technology is assessed by evaluating the cutoff and maximum oscillation frequencies (f/sub T/ and f/sub max/), the minimum noise figure (F/sub min/) and associated power gain (G/sub a/), and the 1/f noise of the devices. Gate-biasing and channel-length and gate-finger-length adjustments are identified as means to optimize the RF performance without any technology process modifications. Changing to N/sub 2/O gate dielectrics is shown to greatly reduce the 1/f noise without sacrificing the AC performance. The power amplifier characteristics of CMOS at low power levels are also discussed.

On-chip interconnect-aware design and modeling methodology based on high bandwidth transmission line devices

This paper expands the on-chip interconnect-aware methodology for high-speed analog and mixed signal design, presented in D. Goren et al. (2002), into a wider class of designs, including dense layout CMOS design. The proposed solution employs a set of parameterized on-chip transmission line (T-line) devices for the critical interconnects, which is expanded to include coplanar structures while considering the silicon substrate effect. The generalized methodology contains treatment of the crossing line effects at the various design stages, including two way interactions between the post layout extraction tool and the T-line devices. The T-line device models are passive by construction, easily migratable among design environments, and allow for both time and frequency domain simulations. These models are verified by S-parameter measurements up to 110GHz, as well as by EM solver results. It is experimentally shown that the effect of properly designed discontinuities is negligible in most practical cases. The basic on-chip T-line methodology is being used extensively for numerous high-speed designs.

Proton radiation response of SiGe HBT analog and RF circuits and passives

Presents the first experimental results of the effects of 63 MeV proton irradiation on SiGe heterojunction bipolar transistor (HBT) analog and radio-frequency (RF) circuits and passive elements. A SiGe HBT bandgap, reference circuit, commonly used to generate stable on-chip voltages in analog ICs, a SiGe HBT voltage-controlled oscillator, a key building block for RF transceivers, and an LC bandpass filter routinely used in RF circuit design were each irradiated to proton fluences as high as 5/spl times/10/sup 13/ p/cm/sup 2/. The degradation associated with these extreme proton fluences was found to be minimal, suggesting that SiGe HBT technology is robust for these types of circuit applications.

Technology Scaling and Device Design for 350 GHz RF Performance in a 45nm Bulk CMOS Process

Power gain (f_MAX) of 350 GHz and cut-off frequency (f_T) of 280 GHz is demonstrated for 36 nm L_poly devices in a 45 nm bulk CMOS process. A record f_T of 350 GHz (intrinsic f_T 425 GHz), without any loss of f_MAX is seen in 28 nm L_poly devices. Combination of advanced lithography and liner stress effect can be leveraged to further boost f_T and f_MAX by 14% with a relaxed pitch device. Comparison with 90 and 65 nm nodes illustrates the impact of scaling and parasitics.

RFCMOS technology from 0.25/spl mu/m to 65nm: the state of the art

The effort to design RF circuits in CMOS is motivated by low cost and significant capacity for on-chip integration. We discuss some of the challenges of implementing RF designs in CMOS, focusing on those introduced by the changing properties of FETs as technology nodes scale and devices shrink. We present methods and tools, using which, designers can ease these challenges and reduce the risk of implementing RF circuits in CMOS.

Design automation methodology and rf/analog modeling for rf CMOS and SiGe BiCMOS technologies

The rapidly expanding telecommunications market has led to a need for advanced rf integrated circuits. Complex rf- and mixed-signal system-on-chip designs require accurate prediction early in the design schedule, and time-to-market pressures dictate that design iterations be kept to a minimum. Signal integrity is seen as a key issue in typical applications, requiring very accurate interconnect transmission-line modeling and RLC extraction of parasitic effects. To enable this, IBM has in place a mature project infrastructure consisting of predictive device models, complete rf characterization, statistical and scalable compact models that are hardware-verified, and a robust design automation environment. Finally, the unit and integration testing of all of these components is performed thoroughly. This paper describes each of these aspects and provides an overview of associated development work.