Joanna Rosner

Chip-to-chip optical interconnects

Terabus is based on a silicon-carrier interposer on an organic card containing 48 polymer waveguides. We have demonstrated 4times12 arrays of low power optical transmitters and receivers, operating up to 20 Gb/s and 14 Gb/s per channel respectively

Silicon Carrier with Deep Through-Vias, Fine Pitch Wiring and Through Cavity for Parallel Optical Transceiver

The design, fabrication, assembly and characterization of a novel silicon carrier package used for enabling a Tb/s parallel optical transceiver is reported. Electrical through-vias, high speed wiring and a through cavity for housing optoelectronic (OE) devices are critical features of the silicon carrier that allow high density integration of optical and electrical components on a single substrate, resulting in a small form factor system that is capable of meeting high bandwidth requirements of large computing systems. A novel hierarchical approach involving eutectic AuSn and SnPb solder systems and flip chip bonding technology is used to assemble the transceiver module. The optical system used for coupling light from the OE devices to waveguides is based on a relay lens that is integrated into the OE array. The measurement and model for alignment tolerance analysis showed constant coupling efficiency from the OE to waveguide over a range of plusmn 10 mum, giving an excellent margin for alignment. Electrical simulations and measurement of silicon carrier through-vias showed an insertion loss of better than 1 dB at 20 GHz. Simulations and measurements also exhibited an attenuation of 4.3 dB/cm at 20 GHz for high speed wiring on the silicon carrier, which was adequate for 20 Gbps data transmission over a channel length of 7 mm

Terabus: a chip-to-chip parallel optical interconnect

Terabus is based on a chip-like optoelectronic packaging structure (Optochip) assembled directly onto an organic card with integrated waveguides (Optocard). To-date, Terabus has demonstrated 4times12-array optical transmitters and receivers operating up to 20 Gb/s and 14 Gb/s per channel

Fabrication challenges for next-generation devices: Microelectromechanical systems for radio-frequency wireless communications

With wireless communications becoming an important technology and growth engine for the semiconductor industry, many semiconductor companies are developing technologies to differentiate themselves in this area. One means of accomplishing this goal is to find a way to integrate passive components, which currently make up more than 70% of the discrete components in a wireless handset, directly on-chip thereby greatly simplifying handsets. While a number of technologies are being investigated to allow on-chip integration, microelectromechanical systems technologies are an important part of this development effort. They have been used to create switches, filters, local oscillators, variable capacitors, and high-quality inductors, to name a few examples. The lithography requirements for these devices are very different than those found in standard semiconductor fabrication with the most important involving patterning over extreme topography. We discuss some of the fabrication challenges for these devices as well as some approaches that have been demonstrated to satisfy them.

Thermal impedance measurements of junction-down mounted single-side contact laser diodes

We designed and fabricated a 10 Gb/s edge-emitter DFB InP laser diode emitting at 1310 nm, and having the anode (p) and cathode (n) contacts fabricated on the same surface as the lasers ridge. This was made possible by epitaxially incorporating a buried contact layer under the laser ridge. The buried contact layer was designed to provide a similar series resistance as is typically obtained with a backside substrate contact. High-speed small-signal and large-signal measurements of the laser diode showed good 10 Gb/s operation. The thermal impedance of this single-side contact edge-emitting laser diode (SSC-LD) was measured using different mounting schemes. Primarily, a junction-down mounting was compared with a junction-up mounting and was found to have lower thermal impedance when the laser ridge was attached to the silicon optical bench (SiOB). The layout of the pads to which the laser diode bonded was also found to impact the thermal impedance, with the ridge contact being the major contributor to lowering the thermal impedance. Three variants of the laser were built with the active region spaced at different distances from the top of the ridge. We show that in the case of junction-down mounting the proximity of the lasers active region to the heat sink strongly affects the measured thermal impedance. 3D thermal simulations agreed well with the measured data and were used to estimate the variations in the thermal impedance due to laser diode bonding misalignment and amount of solder compression.

Silicon optical bench for high-speed optical subassemblies [optical receiver]

A passively aligned, flip-chip receiver optical subassembly (ROSA) was developed. The design features a silicon v-groove with a metallized reflector and a photodiode with an offset active area. This design minimizes the optical path length, allowing for much smaller photodetector areas than those used in previous designs. Excellent performance in terms of coupling efficiency, small signal bandwidth and 10 Gb/s eye diagrams for detectors as small as 20 /spl mu/m in diameter are described. Mechanical features on the bench included special structures for optical underfill, fiber attachment and strain relief.

Fabrication challenges for next-generation devices: MEMS for rf wireless communications

With wireless communications becoming an important technology and growth engine for the semiconductor industry, many semiconductor companies are developing technologies that differentiate themselves in this space. One means of accomplishing this goal is to find a way to integrate passive components, which currently make up over 70 percent of the discrete components in a wireless handset today, directly on-chip thereby greatly simplifying handsets. While a number of technologies are being investigated to allow on- chip integration, MEMS technologies are an important part of this development effort. They have been used to create switches, filters, local oscillators, variable capacitors and high quality factor inductors to name a few examples. The lithography requirements for these devices are very different than those found in standard semiconductor fabrication with the most importatnt involving pattern over extreme topography. In this paper, we discuss some of the fabrication challenges for these devices as well as some approaches that have been demonstrated to satisfy them.