David L. Kencke

The Impact of Thermal Boundary Resistance in Phase-Change Memory Devices

Thermal conduction governs the writing time and energy of phase-change memory (PCM) devices. Recent measurements demonstrated large thermal resistances at the interfaces of phase-change materials with neighboring electrode and passivation materials. In this letter, electrothermal simulations quantify the impact of these resistances on the set to reset transition. The programming current decreases strongly with increasing boundary resistance due to increased lateral temperature uniformity, which cannot be captured using a reduced effective conductivity in the phase-change material. Reductions in programming current from 20% to 30% occur for an interface resistance of 50 m2middotK/GW. The precise spatial distribution of thermal properties is critical for the simulation of PCM devices.

Integration of Back-Gate doping for 15-nm node floating body cell (FBC) memory

Key process features of a scaled, high-performance planar FBC memory fabricated on 25-nm undoped Si and 10-nm BOX SOI substrates are presented. Back-Gate (BG) doping process is revealed to be a critical part of the FBC integration. BG dopant loss due to oxidation and high-temperature processes is minimized to enable high performance at scaled diffusion widths (W<100 nm). Integrating BG doping processes and designing tips and source/drain, we demonstrate a memory retention of over 1 sec (@ 3-µA sensing window) in scaled cells (Lg=50 nm, W=85 nm) suitable for 15-nm technology node.

Floating Body Cell with Independently-Controlled Double Gates for High Density Memory

An aggressively scaled, self-aligned, independently controlled double-gate floating body cell (IDG FBC) is reported. This structure eases the scaling constraints of other FBC memory devices proposed to date. Enhanced memory performance has been demonstrated owing to the independent back gate with thin oxide and thin Si fin. Memory devices with 85-nm Lg and 30-nm fin widths (Z) have been shown to exhibit better memory characteristics at a lower voltage than alternative FBC structures at comparable dimensions. Design, fabrication, operation, and scalability of IDG FBC devices are discussed

A scaled floating body cell (FBC) memory with high-k+metal gate on thin-silicon and thin-BOX for 16-nm technology node and beyond

A scaled, undoped, thin-BOX, planar FBC technology is demonstrated for the first time, featuring 10-nm BOX, 25-nm SOI, high-k, metal gate, separate back-gate (BG) doping, and raised source-drain epitaxy. Retention of a minimum 3-muA sensing window for 100 ms, in devices with 60-nm gate-length (Lg) and 70-nm diffusion width (W), represents the best retention time of all sub-100-nm FBC devices. FBC scaling is predicted to be feasible at least to 40-nm Lg, enabling memory cell sizes much smaller than 6T-SRAM at 16-nm technology node. Functional 32-nm Lg devices suggest the feasibility at the 11-nm technology node.

Floating body cell (FBC) memory for 16-nm technology with low variation on thin silicon and 10-nm BOX

A scaled planar FBC technology with undoped-body is demonstrated featuring 10-nm BOX, 25-nm SOI, high-k and metal gate. Good agreement on retention window characteristics between measured data and simulations is achieved at multiple temperatures and illustrates Shockley-Read-Hall (SRH) recombination and generation dominated loss mechanism during hold condition. Optimization of Source-Drain (SD) and TIP implants are critical for achieving the balance between long retention time and large memory signal. For a minimum 3-muA sensing window, worst-case disturb retention of 25 ms is shown in scaled devices with 55 nm gate-length (LG) and 65 nm width (W). FBC scaling is predicted to be feasible at 16-nm technology node, enabling memory cell sizes much smaller than 6T-SRAM.

Floating-Body Diode—A Novel DRAM Device

A novel 8F2 DRAM cell is introduced, consisting of two gates controlling a low-doped silicon-on-insulator channel and opposite-polarity source and drain. Simulation with models calibrated to experimental floating-body cell data confirms virtual thyristor memory operation and demonstrates 85°C retention time in excess of 10 ms in a scaled FinFET architecture. With unit cell area comparable to that of conventional DRAM, 1.6-V total operation range, 1-ns program time, and CMOS-compatible process, floating-body diode is a candidate for stand-alone or embedded memory applications at 15-nm node and beyond.

The Role of Interfaces in Damascene Phase-Change Memory

Phase change memory (PCM) research has largely focused on bulk properties to evaluate cell efficiency. Now both electrical and thermal interface resistances are characterized and shown to be critical for understanding power in a novel damascene-GST cell. Interfaces reduce reset power 20% and reset current 40% and allow reset current to scale faster than it would without interfaces.

Challenges for on-chip optical interconnects

As integrated circuit interconnect dimensions continue to shrink and signaling frequencies increase, interconnect performance degrades. The performance degradation is due to several factors such as power consumption, cross-talk, and signal attenuation. On-chip optical interconnects are a potential solution to these scaling issues because they offer the promise of providing higher bandwidth. In this paper, progress on the major on-chip optical building blocks will be reviewed. It will be shown that significant advances have been made in the design and fabrication of waveguides, detectors, and couplers. However, major challenges in high speed electrical to optical conversion and signaling remain.

High-speed CMOS-compatible photodetectors for optical interconnects

We have developed high-speed germanium (Ge) photodetectors using standard complementary metal-oxide-semiconductor (CMOS) process technology. We describe the design considerations that led to the devices reported on here. We have characterized these detectors in terms of the following detector metrics: speed, responsivity, dark current and capacitance. The photodetectors exhibit responsivities greater than 0.2 A/W at both 850 and 1550 nm, making them compatible with both long- and short-haul communication systems. Impulse response measurements at both of the above wavelengths indicate 3 dB cutoff frequencies greater than 10 GHz and open eye diagrams have been measured at 20 Gb/s. Dark currents are on the order of 10 to 1000 μA at a bias of 1 V depending on device size. Capacitances measured were on the order of 0.1-10 fF. The performance of the detectors indicates that they are suitable for high speed on-chip optical links. Device simulation models indicate that the fundamental upper limit on the speed of the devices, based on ideal material properties, is high enough to support a number of process generations. Calibration of the models to our experimental data is presented, and areas for improvement are defined.

A multilevel approach toward quadrupling the density of flash memory

A multilevel scheme is presented that explores the possibility of quadrupling flash EEPROM storage density. Sixteen levels (4 bits/cell) of charge are stored in existing NOR stacked gate devices. A distinction is made between logical threshold voltages (as seen by the sense amplifier) and transistor threshold voltages (as defined by the gate characteristics), and precise programming gives distinct logical threshold voltage distributions, whereas transistor threshold voltage distributions are contained in a small 2.5 V range and kept low so that logical distributions survive a ten-year equivalent data retention bake.